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photometric front end data sheet adpd103 rev. b document feedback informati on furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 C 2016 analog devices, inc. all rights reserved. technical support www.analog.com features multi function photometric front end fully i ntegrated afe, adc, led d river s , and timing core usable in a broad range of optical measurement applications, including p hotoplethysmography enables best - in - class ambient light rejection capability witho ut the need for photodiode optical filters three 8 ma to 250 ma led d river s separate data registers for each led / photodiode combination 1 to 8 optical inputs flexible , multiple , shor t led pulses per optical sample 20 -b it burst accumulator enabling 20 bits per sample period on - board sample to sample accumulator , enabling up to 27 bits per data read low power operation i 2 c interface and 1.8 v analog/digital core flexible sampling frequency ranging from 0.1 22 hz to 3.820 k hz fifo d ata operation applications body worn health and fitness monitors , for example, h eart rate monitoring clinical measurements, for example, sp o 2 industrial monitoring background light mea sure ments general description the adpd103 is a highly efficient photometric front end with an integrated 14 - bit analog - to - digital converter ( adc ) and a 20- bit burst accumulator that works in concert with flexible light emitting diode ( led ) driver s. it is designed to stimulate a n led and m easure the corres ponding optical return signal. the data output and functional configuration occur over a 1.8 v i 2 c interface. the control circuitry includes flexible led signaling and synchronous detection . the analo g front end (afe) features best - in - cla ss rejection of signal offset and corruption due to modulated interfere nce commonly caused by ambient light. couple t he adpd103 wit h a low capacitance photodiode of <100 pf for optimal performanc e. the adpd103 can be used with any led.
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adpd103 data sheet rev. b | page 2 of 52 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functi onal block diagram .............................................................. 3 specifications ..................................................................................... 4 temperature and power specifications ..................................... 4 performance specifications ......................................................... 5 analog specifications ................................................................... 6 digital specifications ................................................................... 7 timing specifications .................................................................. 8 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 recommended soldering profile ............................................... 9 esd caution .................................................................................. 9 pin configurations and function descriptions ......................... 10 typical performance characteristics ........................................... 12 theory of operation ...................................................................... 13 i ntroduction ................................................................................ 13 dual time slot operation ......................................................... 13 time slot switch ......................................................................... 14 a djustable sampling frequency ............................................... 15 state machine operation ........................................................... 16 normal mode operation and data flow ................................ 16 afe operation ............................................................................ 18 afe integration offset adjustment ......................................... 18 i 2 c serial interface ..................................................................... 20 typical connection diagram ................................................... 21 led driver pins and led supply voltage .............................. 23 led driv er operation ............................................................... 23 determining the average current ........................................... 23 determining c vled ..................................................................... 23 led inductance considerations .............................................. 24 recommended start - up sequence .......................................... 24 reading data ............................................................................... 24 clocks and timing calibration ................................................ 26 calculating current consumption .......................................... 27 optimizing snr per watt ......................................................... 27 single afe channel mode ......................................................... 28 tia_adc mode ......................................................................... 28 digital integrate mode ............................................................... 30 register listing ............................................................................... 34 led control registers ............................................................... 38 afe configuration reg isters .................................................... 41 system registers ......................................................................... 46 adc registers ............................................................................ 50 data registers ............................................................................. 51 outline dimensions ....................................................................... 52 ordering guide .......................................................................... 52 revision history 2/ 16 rev ision b: initial version
data sheet adpd103 rev. b | page 3 of 52 functional block dia gram led3 driver led2 driver analog block time slot a data time slot b data digital datapath and interface control led3 level and timing control led2 level and timing control led1 driver led1 level and timing control sda scl int dgnd agnd vref 1f avdd dvdd adpd103 14-bit adc tia tia tia tia afe: signal conditioning afe: signal conditioning afe: signal conditioning afe: signal conditioning pdc time slot switch pd1 pd8 pd5 pd2 pd6 pd3 pd7 pd4 ledx1 ledx2 ledx3 lgnd v led pdso led1 led2 led3 v bias bpf 1 integrator v bias bpf 1 integrator v bias bpf 1 integrator v bias bpf 1 integrator 12722-001 b a slot select afe configuration fig ure 1. typical functional block diagram
adpd103 data sheet rev. b | page 4 of 52 specifications temperature and power specification s table 1. operating c onditions parameter test conditions/comments min typ max unit temperature range operating range ?40 + 85 c storage range ?65 +150 c power supply voltages v dd applied at the avdd and dvdd pins 1.7 1.8 1.9 v avdd = dvdd = 1.8 v, ambient temperature, unless otherwise noted. table 2. current consumption 1, 2 parameter symbol test conditions/comments min typ max unit power supply (v dd ) current v dd supply current led _ offset = 25 s; led_period =19 s; led peak current = 25 ma, 4 channels active 1 pulse 100 hz d ata rate; time slot a only 106 a 10 0 hz data rate; time slot b only 94 a 100 hz data rate; both time slot a and time slot b 151 a 10 pulses 10 0 hz data rate; time slot a only 258 a 10 0 hz data rate; time slot b only 246 a 100 hz data rate; both time slot a and time slot b 455 a peak v dd supply current (1.8 v) iv dd _ peak 4 - channel operation 9.3 ma 1- channel operation 2.3 ma standby mode current iv dd _ standby 3.5 a v leda and v ledb supply current ave rage supply current v leda or v ledb pe ak led current = 100 ma; led_pulse width = 3 s 1 pulse 50 h z data rate 15 a 100 hz data rate 30 a 200 hz data rate 60 a 10 pulses 50 h z data rate 150 a 100 hz data rate 300 a 200 hz data rate 600 a 1 leda or ledb is one of led1, led2, or led3. v leda or v ledb is one of v led1 , v led2 , or v led3 . 2 v dd is the volta ge applied at the avdd and dvdd pins.
data sheet adpd103 rev. b | page 5 of 52 performance specific ation s a vdd = d vdd = 1.8 v, t a = full operating temperature range, unless otherwise noted. table 3 . parameter test conditions/comments min typ max unit data aquisition resolution single pulse 1 4 bi ts resolution / sample 64 to 255 p ulses 2 0 bi ts resolution/data read 64 to 255 pulses and sample average = 128 27 bits led driver led current slew rate 1 rise slew rate control setting = 0 ; t a = 25 c ; i led = 70 ma 2 40 m a/s s lew rate control setting = 7; t a = 25 c ; i led = 70 ma 1 400 m a/s fall slew rate control setting = 0, 1, 2; t a = 25 c ; i led = 70 ma 3 200 m a/s slew rate control setting = 6, 7; t a = 25 c ; i led = 70 ma 4500 ma/s led peak cur rent led pulse enabled 8 2 5 0 ma driver compliance voltage voltage above ground required for led driver operation 0.2 v led period afe w idth = 4 s 19 s af e w idth = 3 s 17 s sampling frequency 2 time slot a o nly; normal mode; 1 pulse ; offset_leda = 23 s; period_ leda = 19 s 0.122 3 230 hz time slot b only ; normal mode; 1 pulse ; offset_leda = 23 s; period_ leda = 19 s 0.122 3820 hz b oth time s lots; norm al mode; 1 pulse ; offset_leda = 23 s; period_ leda = 19 s 0.122 1 750 hz t ime slot a only ; nor mal mode; 8 pulses ; offset_leda = 23 s; period_ leda = 19 s 0.122 2 257 hz t ime slot b only ; n ormal mode; 8 pulses ; offset_leda = 23 s; period_ leda = 19 s 0.122 2 531 hz bo th time s lots; n ormal mode; 8 pulses ; offset_leda = 23 s; period _ leda = 19 s 0.122 1 1 93 hz cathode pin (pdc) voltage during all sampling periods register 0x54, bit 7 = 0x0; register 0x3c, bit 9 = 1 3 1.8 v r egister 0x54, bit 7 = 0x0; register 0x3c, bit 9 = 0 1 .3 v during slot a sampling register 0x54, bit 7 = 0x1; register 0x54 , bits [9:8] = 0x0 3 1 .8 v r egister 0x54, bit 7 = 0x1; register 0x54 , bits [9:8] = 0x1 1 .3 v r egister 0x54, bit 7 = 0x1; register 0x54 , bits [9:8] = 0x2 1 .55 v register 0x54 , bit 7 = 0x1; register 0x54 , bits [9:8] = 0x3 4 0 v during slot b sampling register 0x54, bit 7 = 0x1; register 0x54 , bits [11:10] = 0x0 3 1 .8 v register 0x54, bit 7 = 0x1; register 0x54 , bits [11:10] = 0x1 1.3 v r egister 0x54, bit 7 = 0x1; register 0x54 , bits [11:10] = 0x2 1 .55 v r egister 0x54, bit 7 = 0x1; register 0x54 , bits [11:10] = 0x3 4 0 v during sleep periods register 0x54, bit 7 = 0x0; reg ister 0x3c, bit 9 = 1 1.8 v register 0x54, bit 7 = 0x0; register 0x3c, bit 9 = 0 1.3 v register 0x54, bit 7 = 0x1; register 0x54 , bits [13:12] = 0x0 1.8 v r egister 0x54, bit 7 = 0x1; register 0x54[13:12] = 0x1 1 .3 v r egister 0x54, bit 7 = 0x 1; register 0x54[13:12] = 0x2 1 .55 v r egister 0x54, bit 7 = 0x1; register 0x54[13:12] = 0x3 0 v p hoto d iode in put pin s/ anode voltag e during all sampling periods 1.3 v during sleep periods c athode voltage v 1 led inductance is negligible for these values. the effective slew rate slows with increased inductance. 2 the maximum valu es in this specification are the internal adc sampling rates in normal mode. the i 2 c read rate s in some configurations may limit the actual output data rate of the device 3 this mode may induce additional noise and is not recommended unless absolutely necessary. the 1.8 v setting uses v dd , whi ch contains greater amounts of differential voltage noise with respect to the anode voltage. a differential voltage between the anode and cathode injects a differential current across the capacitance of the phot odiode of the magnitude c dv/dt. 4 this setting is not recommended for photodiodes because it causes a 1.3 v forward bias of the photodiode.
adpd103 data sheet rev. b | page 6 of 52 analog specification s av dd = d vdd = 1.8 v, t a = full operating temperature range, unless otherwise noted. compensation of the afe offset is explained in the afe operation section. table 4. parameter test conditions/comments min typ max unit input capacitance 100 pf pulsed signal conversions, 3 s wide led pulse 1 4 s wide afe integration; normal operation, register 0x43 (time slot a) and register 0x45 (time slot b) = 0xada5 adc resolution 2 transimpedance amplifier (tia) feedback resistor 25 k ? 1. 64 na/ lsb 50 k? 0.82 na/ lsb 100 k ? 0. 41 na/ lsb 200 k ? 0. 2 na/ lsb adc saturation level tia feedback resistor 25 k ? 13. 4 a 50 k ? 6. 7 a 100 k ? 3. 35 a 200 k ? 1. 67 a ambient signal headroom on pulsed signal tia feedback resistor 25 k? 37 a 50 k ? 18. 5 a 100 k ? 9. 25 a 200 k ? 4. 63 a pulsed signal conversions, 2 s wide led pulse 1 3 s wide afe integration; normal operation , register 0x43 (time slot a) and register 0x45 (tim e slot b) = 0xada5 adc resolution 2 tia feedback resistor 25 k? 2.31 na/lsb 50 k ? 1. 15 na/ lsb 100 k ? 0. 58 na/ lsb 200 k ? 0. 29 na/ lsb adc saturation level tia feedback resistor 25 k? 18.9 a 50 k ? 9. 46 a 100 k ? 4. 73 a 200 k ? 2. 37 a ambient signal headroom on pulsed signal tia feedback resistor 25 k ? 31. 5 a 50 k ? 15. 7 a 100 k ? 7. 87 a 200 k? 3.93 a full signal conversions 3 tia saturation level of pulsed signal and ambient level tia feedback resistor 25 k ? 50. 4 a 50 k ? 25. 2 a 100 k ? 12. 6 a 200 k ? 6. 3 a
data sheet adpd103 rev. b | page 7 of 52 parameter test conditions/comments min typ max unit system performance total output noise floor normal mode per pulse per channel no led c pd 70 pf 25 k referred to adc input 2. 0 l sb rms 25 k referred to peak input signal for 2 s led pulse 4. 6 na rms 25 k referred to peak input signal for 3 s led pulse 3. 3 na rms 25 k saturation signal - to - noise ratio (snr) per pulse per channel 4 72.3 db 50 k referred to adc input 2. 4 l sb rms 50 k referred to peak input signal for 2 s led pulse 2. 8 na rms 50 k referred to peak input signal for 3 s led pulse 2. 0 na rms 50 k saturation snr per pulse per c hannel 4 70. 6 db 100 k referred to adc input 3. 4 l sb rms 100 k referred to peak input signal for 2 s led pulse 1. 9 na rms 100 k referred to peak input signal for 3 s led pulse 1. 4 na rms 100 k saturation snr per pulse per channel 4 67.6 db 200 k referred to adc input 5. 5 l sb rms 200 k referred to peak input signal for 2 s led pulse 1. 6 na rms 200 k referred to peak inp ut signal for 3 s led pulse 1. 1 na rms 200 k saturation snr per pulse per channel 4 63. 5 db dc power supply rejection ratio (dc psrr) 37 db 1 this saturation level applies to the adc only and , therefore , inclu des only the pulsed signal. any non pulsatile signal is removed prior to the adc stage. 2 adc resolution is listed per pulse when the afe offset is correctly compensated per the afe operation section . if using multiple pulses , divide by the number of pulses. 3 this saturation level applies to the full signal path and , therefore , includes both the ambient signal and the pul sed signal. 4 the noise term of the saturation snr value refers to the receive noise only and does not include photon shot noise or any noi se on the led signal itself. digital specificatio ns d vdd = 1.7 v to 1.9 v , unle ss otherwise noted . table 5 . parameter symbol test conditions/comments min typ max unit logic inputs (scl, sda) input voltage level high v ih 0. 7 d vdd 3. 6 v low v il 0. 3 d vdd v input current level h igh i ih ? 10 + 10 a low i il ? 10 + 10 a input capacitance c in 10 pf logic outputs int output voltage level high v oh 2 ma high level output current d vdd ? 0.5 v low v ol 2 ma low level output current 0.5 v pdso output voltage level high v oh 2 ma high level output current d vdd ? 0.5 v low v ol 2 ma low level output current 0. 5 v sda output voltage level low v ol1 2 ma low level output current 0. 2 d vdd v sda output current level low i ol v ol1 = 0.6 v 6 ma
adpd103 data sheet rev. b | page 8 of 52 timing specification s table 6 . i 2 c timing specifications parameter symbol test conditions/comments min typ max unit i 2 c port 1 s ee figure 2 scl frequency 400 khz minimum pulse width high t 1 600 ns low t 2 130 0 ns start condition hold time t 3 600 ns setup time t 4 600 ns sda setup time t 5 100 ns scl and sda rise time t 6 100 0 ns fall time t 7 300 ns stop condition setup time t 8 600 ns 1 guaranteed by design. sda scl t 3 t 6 t 1 t 5 t 2 t 7 t 3 t 4 t 8 12722-002 f igure 2. i 2 c timing
data sheet adpd103 rev. b | page 9 of 52 absolute maximum rat ings table 7. parameter rating a vdd to agnd ? 0.3 v to + 2.2 v d vdd to dgnd ? 0.3 v to + 2.2 v int to dgnd ? 0.3 v to + 2.2 v pds o to dgnd ? 0.3 v to + 2.2 v led x x to l gnd ? 0.3 v to + 3. 6 v scl to dgnd ? 0.3 v to + 3. 9 v sda to dgnd ? 0.3 v to + 3. 9 v junction temperature 150c esd 28- lead lfcsp human body model (hbm) 1500 v charge device model (cdm) 1250 v machine model (mm) 100 v 16- ball wlcsp human body model (hbm) 1500 v charge device model (cdm) 500 v machine model (mm) 100 v stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operatio n of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistan ce table 8 . thermal resistance package type ja unit 28- lead lfcsp_wq 54.9 c/w 16 - ball wlcsp 60 c/w recommended solderin g profile figure 3 and table 9 provide details about the recommended soldering profile. t p t l t 25c to peak t s preheat critical zone t l to t p temperature time ramp-down ram p-up t smin t smax t p t l 12722-003 f igure 3. recommended soldering profile table 9 . recommended soldering profile profile feature condition (pb -f ree) average ramp rate (t l to t p ) 3c/sec max preheat minimum temperature (t smin ) 150c maximum temperature (t smax ) 200c time (t smin to t smax ) (t s ) 60 sec to 180 sec t smax to t l ramp - up rate 3c/sec maximum time maintained above liquidous temperature liquidous tem perature (t l ) 217c time (t l ) 60 sec to 150 sec peak temperature (t p ) + 260 (+0/?5)c time within 5c of actual peak temperature (t p ) < 30 sec ramp - down rate 6c/sec maximum time from 25c to peak temperature 8 minutes max imum esd caution
adpd103 data sheet rev. b | page 10 of 52 pi n configuration s and function descrip tions int pdso dvdd agnd vref avdd pd1 pd2 pd3 pd4 pdc pd5 pd6 pd7 pd8 nic nic nic nic nic nic sda scl lgnd ledx2 ledx3 ledx1 nic 1 2 3 4 5 6 7 17 18 19 20 21 16 15 8 9 10 11 12 13 14 24 25 26 27 28 23 22 adpd103 top view (not to scale) notes 1. nic = nonbonded pad, can be grounded. 2. exposed pad (digital ground). connect the exposed pad to ground. 12722-004 f igure 4. 28 - lead lfcsp pin configuration table 10. 28- lead lfcsp pin function descriptions pin no. mnemonic type 1 description 1 int do interrupt output . 2 pdso do power - down status output . 3 dvdd s 1.8 v digital supply . 4 agnd s analog ground . 5 vref ref internally generated adc voltage reference. buffer this pin with a 1 f capacitor to a gnd . 6 avdd s 1.8 v analog supply . 7 pd1 ai photodiode current inpu t (anode) . if not in use, leave this pin floating . 8 pd2 ai photodiode current input (anode). if not in use, leave this pin floating. 9 pd3 ai photodiode current input (anode). if not in use, leave this pin floating. 10 pd4 ai photodiode current input (anode). if not in use, leave this pin floating. 11 pd c ao photodiode common cathode bias . 12 pd5 ai photodiode current input (anode). if not in use, leave this pin floating. 13 pd6 ai photodiode current input (anode). if not in use, leave this pin floa ting. 14 pd7 ai photodiode current input (anode). if not in use, leave this pin floating. 15 pd8 ai photodiode current input (anode). if not in use, leave this pin floating. 16 to 22 n i c r not internally connected (nonbonded pad ) . this pin can be ground ed. 23 ledx1 ao led driver 1 current sink . if not in use, leave this pin floating. 24 ledx3 ao led driver 3 current sink . if not in use, leave this pin floating. 25 ledx2 ao led driver 2 current sink . if not in use, leave this pin floating. 26 lgnd s l ed driver ground . 27 scl di i 2 c clock input . 28 sda dio i 2 c data input/ output . e pa d ( dgnd ) s exposed pad ( digital ground ) . connect the exposed pad to ground. 1 do means digital output, s means supply, ref means voltage re ference, ai means analog input, ao means analog output, r means reserved , di means digital input, and dio means digital input/output.
data sheet adpd103 rev. b | page 11 of 52 1 2 3 a b c d e f lgnd ledx2 adpd103 top view, ball side down (not to scale) ledx3 ledx1 sda scl int dvdd dgnd pdso vref avdd pd5-8 pdc pd1-4 agnd 12722-005 f igure 5. 16 - ball wlcsp pin configuration table 11 . 16- ball wlcsp pin function descriptions pin no. mnemonic type 1 description a1 lgnd s led driver ground . a2 ledx2 ao led driver 2 current sink. if not in use, leave this pin floating. b1 ledx3 ao led driver 3 current sink. if not in use, leave this pin floating. b2 ledx1 ao led driver 1 current sink. if not in use, leave this pin floating. b3 sda dio i 2 c data input/ output . c1 scl s i 2 c clock input . c2 int do interrupt output . c3 dvdd s 1.8 v digital supply . d2 dgnd s digital ground . d3 agnd s analog ground . e1 pdso do power - down status output . e2 vref ref internally generated adc voltage reference. buffer this pin with a 1 f capacitor to agnd . e3 avdd s 1.8 v analog supply . f1 pd5 -8 ai p hotodiode c om bined current i nput of pd5 to pd8 . if not in use, leave this pin floating. f2 pdc ao photodiode common cathode bias . f3 pd1 -4 ai photodiode c om bined current i nput of pd1 to pd4 . if not in use, leave this pin floating. 1 s means supply, ao means analog output, dio means digital input/output, do means digital output , ref means voltage reference, and ai means analog input.
adpd103 data sheet rev. b | page 12 of 52 typical performance characteristics 30 0 5 10 15 20 25 ?25 ?20 ?15 ?10 ?5 0 5 10 15 percent of population (%) sample frequency deviation from nominal (%) 12722-006 figure 6 . 32 khz clock frequency distribution (default settings, before user calibration: register 0x4b = 0x2612) 0 5 10 15 20 percent of population (%) frequency (mhz) 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 12722-007 figure 7 . 32 mhz clock frequency distribution (default settings, before user calibration: register 0x4d = 0x42 5e) 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 20 40 60 18016014012010080 noise (na rms) photodiode capacitance (pf) 12722-200 25k 50k 200k 100k figure 8 . input referred noise vs . photodiode capacitance, led p ulse w idth = 3 s 6 5 4 3 2 1 0 0 20 40 60 18016014012010080 noise (na rms) photodiode capacitance (pf) 25k 200k 100k 12722-201 50k f igure 9 . input referred noise vs . photodiode capacitance, led p ulse w idth = 2 s
data sheet adpd103 rev. b | page 13 of 52 theory o f operation intr oduction the adpd103 operates as a complete optical transceiver stimulat ing up to three leds and meas ur ing the return signal on up to eight separate current inputs . the core consists of a photo metric front end coupled with an adc , digital block , and three independent led driver s. the core circuitry stimulates the leds and measures the return in the analog block through one to eight photodiode inputs, storing the results in discrete data location s. the eight inputs are broken into two blocks of four simultaneo us input channels. data can be read directly by a register, or through a fifo . this highly integrated system includes an analog signal processing block, digital signal processing block, i 2 c c ommunication interface, and programmable pulsed led current source s. the led driver is a current sink and is agnostic to le d supply voltage and led type. the photodiode ( pd x) inputs can accommodate any photodiode with an input capacitance of less than 100 p f. the adpd103 is purposefully designed to produce a high sn r for relatively low led power w hile greatly reducing the effect of ambient light on the measured signal. dual time slot opera tio n the adpd103 operates in two independent time slots, time slot a and time slot b, which are carried out sequentially. the entire signal path from led stimulation to data capture and processing is executed during each time slot . each time slot has a separate datapath that uses independent settings for the led driver , afe setu p, and the resulting data. time slot a and time slot b operate in sequence for every sampling period, as shown in figure 10 . t he timing parameters are defined as follows: t a (s) = slota_led_offset + n a slota_led_period where n a is th e number of pulses for time slot a (register 0x31, bits[15:8]). t b (s) = slotb_led_offset + n b s lotb_led_period where n b is the number of pulses for time slot b (register 0x36, bits[15:8]). calculate the led period using the following equation: l ed_period, minimum = 2 afe_width + 11 t 1 and t 2 are fixed and based on the computation time for each slot. if a slot is not in use , these times do not add to the total active time. table 12 defines the values for these led and sampling time parameters . active t a t 1 t b t 2 sleep time slot a time slot b active 1/f sample n a pulses n b pulses 12722-008 f igure 10 . time slot timing diagram table 12. led timing and sample timing parameters parameter register bits test conditions/comments min typ max unit slota_led_offset 1 0x30 [7:0] delay from power - up to leda rising edge 23 63 s slotb_led_offset 1 0x35 [7:0] delay from power - up to ledb rising edge 23 63 s slota_led_period 2 0x31 [7:0] time between led pulses in time slot a ; slotx_ afe_width = 4 s 19 63 s slotb_led_period 2 0x36 [7:0] time between led pulses in time slot b ; slotx_ afe_width = 4 s 19 63 s t 1 c ompute time for time slot a 68 s t 2 c ompute time for time slot b 20 s t sleep s leep time between sample periods 222 s 1 setting the slotx_led_offset below the specified minimum value may cause failure of ambient light rejection for large photodi odes. 2 setting the slotx_led_period below the specified minimum value can cause invalid data ca ptures.
adpd103 data sheet rev. b | page 14 of 52 time slot switch up to eight photodiodes (pd1 to pd8) can be connected to the adpd103 . the photodiode anodes are connected to the pd1 to pd8 input pins; the photodiode cathodes are connected to the cathode pin, pdc. the anodes are assigned in three different configurations depending on the settings of register 0x14 (see figure 11 , figure 12 , and figure 13 ). a switch sets which photodiode g roup is connected during time slot a and time slot b. see table 13 for the time slot switch registers. when using less than eight photodiodes, it is important to leave the unused inputs floating for proper operatio n of the device. the photodiode inputs are current inputs and as such, these pins are also considered to be voltage outputs. tying these inputs to a voltage may saturate the analog block. register 0x14, pd1 to pd8 input configurations ch1 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 input configur a tion for register 0x14[ 1 1:8] = 5 register 0x14[7:4] = 5 ch2 ch3 ch4 12722-109 f igure 11 . pd1 to pd4 connection input configur a tion for register 0x14[ 1 1:8] = 4 register 0x14[7:4] = 4 ch1 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 ch2 ch3 ch4 12722- 1 10 f igure 12 . pd5 to pd8 connection input configur a tion for register 0x14[ 1 1:8] = 1 register 0x14[7:4] = 1 ch1 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 ch2 ch3 ch4 12722- 11 1 f igure 13 . 2-to- 1 pd current summation
data sheet adpd103 rev. b | page 15 of 52 table 13 . time slot switch ( register 0x14) address bit s name description 0x14 [11:8] slotb_pd_sel selects connection of photodiode for time slot b as shown in figure 11 , figure 12, and figure 13 . 0x 0: inputs are float ing in time slot b. 0x 1: all pdx pins ( pd1 to pd8 ) are connected during time slot b. 0x 4: pd5 to pd 8 are connected during time slot b. 0x 5: pd1 to pd 4 are connected during time slot b. o ther: reserved. [7:4] slota_pd_sel selects connect ion of photodiode for time slot a as shown in figure 11 , figure 12 , and figure 13 . 0x 0: inputs are floating in time slot a. 0x 1: all pdx pins ( pd1 to pd8 ) are connected during time slot a. 0x 4: pd5 to pd 8 are connected during time slot a. 0x 5: pd1 to pd 4 are connected during time slot a. other: reserved. adjustable sampling frequency register 0x12 controls t he sampling frequency setting of the adpd103 and register 0x4b, bits [5:0] further tune s this clock for greater accuracy . the sampling frequency is governed by an internal 32 khz sample rate clock that also drives the transitio n of the internal state machi ne. the maximum sampling frequencies for some sample conditions are listed in table 3 . the maximum sample frequency for all conditions is determined by the following equation: f sample, max = 1/( t a + t 1 + t b + t 2 + t sleep, min ) if a given time slot is not in use , elements from that ti m e sl o t do n ot factor into the calculation. for example , if time slot a is not in use, t a and t 1 do not add to the sampling period and the new maximum sampli ng fre quency is calculated as follows: f sample, max = 1/( t b + t 2 + t sleep, min ) where t s l e e p, min is the minimum sleep time required between samples . see the dual time slot operation section for the definitions of t a , t 1 , t b , and t 2 . external sync for sampling the adpd103 provides an option to use an external sync signal to trigger the sampling periods. this external sample sync signal can be provided e ither on the int pin or the pdso pin. this functionality is controlled by register 0x4f, bit s [3:2]. when enabled , a rising edge on the selected input specifies when the nex t sample cycle occurs. when triggered , there is a delay of one to two internal sampl ing clock (32 k hz) cycles , and then the normal start - up sequence occurs. this sequence is the same as if the normal sample timer provided the trigger . to enable the external sync signal feature, use the following procedure : 1. write 0x 1 to register 0x10 to enter program mode. 2. write the appropriate value to regi ster 0x4f, bits [3:2] to select whether the int pin or the pdso pin specifies whe n t he next sample cycle occur s. also, enable the appropriate input buffer using register 0x4f, bit 1 , for the int pin , or register 0x4f, bit 5 , for the pdso pin. 3. write b1 to ext_sync_ena, r egister 0x38 , b it 14 to enable the external sampling trigger. 4. write 0x2 to register 0x10 to start the sampling operation s. 5. a pply the external sync signal on the s elected pin at th e d esire d rate; sampling occur s at that rate. as with normal sampling operations, read t he data using the fifo or the data registers . the maximum frequency constraints also apply in this case . providing an external 32khz clock the adpd103 has an option for the user to provide an external 32 khz clock to the device for system synchronization or for situations where a clock with better accuracy than the internal 32 khz clock is required. the external 32 k hz clock is provided on the pdso pin. to enable the 32 khz external clock, use the following procedure at startup : 1. drive the pdso pin to a valid logic level or with the desired 32 khz clock prior to enabling the pdso pin as an input. do not leave the pin f loating prior to enabling it. 2. wr ite b 1 to register 0x4f , b it 5 to enable the pdso pin a s a n input. 3. write b11 to r egister 0x4b , bit 7 and bit 8 ( clk32k_en and clk32k_byp , respectively) to configure the device to use an external 32 khz clock. 4. write 0x1 to register 0x10 to enter program mode. 5. write additional control registers in any order while the device is in program mode to configure the device as required. 6. write 0x2 to register 0x10 to start the normal samplin g op eration.
adpd103 data sheet rev. b | page 16 of 52 state machine operation during each time slot, the adpd103 operates according to a state machine. the state machine operates in the following sequence, shown in figure 14 . standby register 0x10 = 0x0000 ultralow power mode no data collection all register values are retained. program register 0x10 = 0x0001 safe mode for programing registers no data collection device is fully powered in this mode. normal operation register 0x10 = 0x0002 leds are pulsed and photodiodes are sampled standard data collection device power is cycled by internal state machine. 12722-016 f igure 14 . state machine operation flowchart the adpd103 operates in one of three modes: standby, program, and normal sampling mode. standby mode is a power saving mode in which no data collection o ccurs. all register values are retained in this mode. to place the device in standby mode, write 0x0 to register 0x10, bits[1:0]. the device powers up in standby mode. program mode is used for programming reg isters. always cycle the adpd103 through program mode when writing registers or changing modes. because no power cycling occurs in this mode, the device may consume higher current in program mo de than in normal operation. to place the device in program mode, write 0x1 to register 0x10, bits[1:0]. in normal operation, the adpd103 pulses light and collects data. power consumption in th is mode depends on the pulse count and data rate. to place the device in normal sampling mode, write 0x2 to register 0x10, bits[1:0]. normal mode operation and d ata flow in normal mode, the adpd 103 follows a speci fic pattern set up by the state machine. this pattern is shown in the corresponding data flow in figure 15. the pattern is as follows: 1. led pulse and sample .t he adpd103 pulses external leds. the response of a photo diode or photodio des to the reflected light is measured by the adpd103 . each data sample is constructed from the sum of n indiv idual pulses , where n is user configurable between 1 and 255. 2. in ter s ample a veraging . i f desired, the logic can average n sa mples, from 2 to 128 in powers of 2 , to produce output data. new output data is saved to the output registers every n samples. 3. data read . t he host processor reads the converted results from the data register or the fifo. 4. repeat. the sequence has a few different loops that enable different types of av eraging while keeping both time slot s c lose in time relative to each other. sample 1: time slot b 16 bits [14 + log 2 (n a )] bits up to 20 bits [14 + log 2 ( n a n a )] bits up to 27 bits [14 + log 2 ( n b n b )] bits up to 27 bits time slot b time slot a 16-bit clip if val (2 16 ? 1) val = val else val = 2 16 ? 1 n a notes 1. n a and n b = number of led pulses for time slot a and time slot b. 2. n a and n b = number of averages for time slot a and time slot b. 16 bits [14 + log 2 (n b )] bits up to 20 bits 16-bit clip if val (2 16 ? 1) val = val else val = 2 16 ? 1 n b 1 n b adc offset [14 + log 2 (n a )] bits up to 22 bits sample 1: time slot a sample n b : time slot b sample n a : time slot a 14 bits 14 bits 20-bit clip if val (2 20 ? 1) val = val else val = 2 20 ? 1 n a n a 14-bit adc 1 n a 1 n a fifo 32-bit data registers 16-bit data registers 12722-009 0 1 0 1 register 0x11[13] figure 15 . adpd103 datapath
data sheet adpd103 rev. b | page 17 of 52 led pulse and sample at each sampling p eriod, the selected led driver drives a series of led pulses, as shown in figure 16. the magnitude, duration, and number of pulses are programmable over the i 2 c interface . each l ed pulse coincides with a sensing period so that the sensed value represents the total charge acquired on the photodiode in response t o only the corresponding led pulse. charge, such as ambient light, that does not correspond to the led pulse is rejected. after each led pulse , the photodiode output relating the pulsed led signal is sampled and converted to a digital value by the 14- bit a dc. each subsequent conversion within a sampling period is summed with the previous result. up to 255 pulse values from the adc can be summed in an individual sampling period. there is a 20 - bit maximum range for each sampling period. averaging the adpd103 offer s sample accumulation and averaging functionality to increase signal resolution. within a sampling period , the afe can s um up to 256 sequential pulses. as shown in figure 15 , s amples acquired by the afe are clipped to 20 bits at the output of the afe. additional resolution , up to 27 bits, can be achieved by averaging between sampl ing periods . this accumulated data of n samples is stored as 27 - bit values and can be read out directly by using the 32 - bit output registers or the 32 - bit fifo configuration. when using the averaging feature set up by the register, subsequent pulses can be averaged by powers of 2. the user can select from 2, 4, 8 up to 128 samples to be a veraged. pulse data is still acquired by the afe at the sampling frequency, f sample (register 0x12), but new data is written to the registers at the rate of f sample /n e very n th sample. this new data consists of the sum of the previous n samples. the full 3 2- bit sum is stored in the 32 - bit registers. however, b efore sending this data to the fifo , a divide by n operation occurs. this divide operation mainta ins bit depth to prevent clipping on the fifo. use t his between sample averaging to lower the nois e whil e maintaining 16 - bit resolution. if the pulse count register s are kept to 8 or less, the 16 - bit width is never exceeded. therefore, when using register 0x15 to average subsequent pulses, many pulses can be accum ulated without exceeding the 16 - bit word widt h. this can reduce the number of fifo reads required by the host processor. data read the host processor reads output data from the adpd103 , via the i 2 c protocol, from the data registers or fro m the fifo. new output data is made available every n samples, where n is the user configured averaging factor . the averaging factors for time slot a and time slot b are configurable independently of each other. if they are the same, both time slots can be configured to save data to the fifo. if the two averaging factors are different, o nly one time slot can save data to the fifo; data from the other time slot can be read from the output registers. the data read operations are described in more detail in th e reading data section. 0 0.5 1.0 1.5 2.0 2.5 3.0 time (s) optical sampling locations number of led pulses ( n a or n b ) led current (i led ) shown with f sample = 10 hz 12722-010 f igure 16 . example of a photoplethysmography ( ppg ) signal sampled at a data rate of 10 hz using five pulses per sample
adpd103 data sheet rev. b | page 18 of 52 afe operation the timing within each pulse burst is important for optimizing the operation of the adpd103 . figure 17 shows the timing wave - form s for a single time slot as an led pulse respo nse propagates through the analog block of the afe. the first graph, shown in green, shows the ideal led pulsed output. the filtered led response, shown in blue, shows the ou tput of the analog integrator. the thir d graph, shown in orange, illustrates an op timally placed integration window . when programmed to the optimized value , the full signal of the filtered led response can be integrated . the afe integration window is then applied to the output of the band - pass filter ( bpf ) and the result is sent to the adc and summed for n pul ses. if the afe window is not correctly sized or located , all of the receive signal is not properly r eported and system perfor - mance is not optimal ; therefore, it is important to verify proper afe position for every new hardware des ign or the led width. afe integration offs et adjustment the afe integration width must be equal or larger than the led width. as afe width increases, the output noise increases and the a bility to suppress high frequency content from the environ - ment decreases. it is therefore desirable to keep the afe integration width small. however, if the afe width is too small, the led signal is attenuated. with most hardware selections, the afe width produces the optimal snr at 1 s more than the led width. after setti ng led width, led offset, and afe width, the adc offset can then be optimized. the afe offset must be manually set such that the falling edge of the first segment of the integration window matches the zero crossing of the filtered led response. f igure 17 . afe operation diagram
data sheet adpd103 rev. b | page 19 of 52 afe integration offset starting point the starting point of this offset, as expressed in microseco nds , is set such that the falling edge of the integration window aligns with the falling edge of the led . led_falling_edge = led_offset + led_width and, afe_integration_falling_edge = 9 + afe_offset + afe_width if both falling edges are set equal to each other, solve for afe_offset to obtain the following equation: afe_offset_starting_point = led_offset + le d_width ? 9 ? afe_width setting the afe offset to any point in time earlier than the starting point is equivalent to setting the integration in the future; the afe cannot integrate the result from an led pulse that has not yet occurred. as a result, an afe_offset value less than the afe_offset_starting_point is an erroneous setting. such a result may indicate that current in the tia is operating in the reverse direction from the intended schematic, where the led pulse is causing the current to leave the tia rather than enter it. because, for most setups, the afe_width is 1 s wider than the led_width, the afe_offset_starting_point value is typically 10 s less than the led_offset value. any value less than led_offset C 10 is erroneous. the optimal afe offset is som e time after the afe_offset_starting_ point. the band - pass filter response, led response, and photodiode response each add some delay. in general, the com - ponent choice, board layout, led_offset, and led_width are the variables that can change the afe_offs et. after a specific design is set, the afe_offset can be locked down and does not need to be optimized further. sweeping the afe position the afe offsets for time s lot a and time s lot b are controlled by bits[10:0] of register 0x39 and register 0x3b , resp ectively. each lsb represents one cycle of the 32 mhz clock, or 31.25 ns. the register can be thought of as 2 11 ? 1 of these 31.25 ns steps, or it can be broken into an afe_co a rse setting using bits [10:5] to represent 1 s steps and bits [4:0] to represent 31.25 ns steps. sweeping the afe position from the starting point to find a local maximum is the recommended way to optimize the afe offset. the setup for this test is to allow the led light to fall on t he photodiode in a static way. this is typical ly done with a reflectin g surface at a fixed distance. the afe position can then be swept to look fo r changes in the output level. when adjusting the afe position , it is important to sweep the position using the 31.25 ns steps. typically, a local maximum is found within 2 s of the starting point for most systems. figure 18 shows an ex ample of an afe sweep, where 0 on the x - axis represents the afe s tarting point defined previously. each data point in the plot corresponds t o one 31.25 ns step of the afe_ offset. the optimal location for afe_ offset in this example is 0.687 s from the afe starting point. 0.687 100 95 90 85 80 75 relative output value (%) afe offset from starting point (s) 12722-113 0 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 f igure 18 . afe sweep example table 14 lists some typic al led and afe values after optimization. in general , it is not recommended to use the afe_ offset n umbers in table 14 without first verifying them against the afe sweep method . repeat t his method for every new led width and with every new set of hardware made with the adpd103 . for maximum accuracy, i t is recommended that the 32 mhz clock be calibrated prior to sweeping the afe . table 14. afe window settings led register 0x30 or register 0x35 afe register 0x39 or register 0x3b comment 0x0219 0x19f b 2 s led pulse, 3 s afe width, 25 s led delay 0x0319 0x21f4 3 s led pulse, 4 s afe width, 25 s led delay
adpd103 data sheet rev. b | page 20 of 52 i 2 c serial interface the adpd103 supports an i 2 c serial interface via the sda (data) and scl (clock) pins . all internal registers are accessed through the i 2 c interface. the adpd103 conforms to the um10204 i 2 c- bus specification and user manual , rev. 05 9 october 2012, available from nxp semico nductors. it supports a fast mode (400 kbps) data transfer. re gister read and write are supported, as shown in figure 19. figure 2 shows the timing diagram for the i 2 c interface. slave ad dress the default 7- bit i 2 c slave address for the device is 0x64, followed by the r/ w bit . for a write, the default i 2 c slave address is 0xc8; for a read, the default i 2 c address is 0xc9. the slave address is configurable b y writing to re gister 0x 0 9, bits[7:1]. when multiple adpd103 devices are on the same bus lines , the int and pdso pins can be used to select specific devices for the address change. register 0x0d can be used to select a key to enable address change s in specific devices. use the following procedure to change the slave address when multiple adpd103 devices are connected to the same i 2 c bus lines: 1. usin g register 0x4f , e nab le the input buffer of the pdso pin, the int pin , or both , depending on the key being used. 2. for the device identified as requiring an address change, set the int and/or pdso pins high or low to match the key being used. 3. write the slave_address_key using register 0x 0d , bi ts [15:0] to match the desired function. the allowed key s a re shown in table 24. 4. write the desired slave_address using register 0x 09 , bi t s [7:1]. while writing to register 0x 0 9, bits[7:1] , write 0 xad to register 0x 0 9, bit[15:8] . register 0x 0 9 must b e wr itten to immediately after writing to register 0x 0 d. 5. repeat step 1 to step 4 for all the devices that need the slave_address changed. 6. set the int and pdso pins as desired for normal operation using t he new slave_address for each device. i 2 c write and read operations figure 19 illustrates the adpd103 i 2 c write and read operations . single word and mu ltiword read operations are supported. for a single register read, the host sends a no acknowledge after the second data byte is read and a new register address is needed for each access. for multiword operations, each pair of data bytes is followed by an acknowledge from the host until the last byte of the last word is read. the host indicates the last read word by sending a no acknowledge. when reading from the fifo (register 0x60) , the data is automatically advanced to the next word in the fifo and the space is freed. when reading from other registers, the register address is automatically advanced to the next register, except at register 0x5f or register 0x7f, where the address does not increment. this allows lower overhead reading of sequential registe rs. all register writes are single word only and require 16 bits (one word) of data. the software reset (register 0x 0f , bit 0 ) is the only command that does not return an acknowledge because the command is instantaneous . table 15 . definition of i 2 c terminology term description scl serial clock. sda serial address and data. master the master is the device that initiates a transfer, generates clock signals, and terminates a transfer. slave the slave is the device addressed by a master. the adpd103 operates as a slave device. start (s) a high to low transition on the sda line while scl is high; all transactions begin with a start condition. start (sr) repeated start condition. stop (p) a low to high transition on the sda line while scl is high. a stop condition terminates all transactions. ack during the acknowledge or no acknowledge clock pu lse, the sda line is pulled low and remains low. nack during the acknowle dge or no acknowledge clock pulse, the sda line remains high. slave address after a start (s), a 7 - bit slave address is sent, which is followed by a data direction bit (read or write). read (r) a 1 indicates a request for data. write (w) a 0 indicates a transmission.
data sheet adpd103 rev. b | page 21 of 52 notes 1. the shaded areas represent when the device is listening. master start slave address + write register address slave ack ack ack ack master start sr slave address + write register address ack/nack stop slave ack ack data[7:0] register write data[15:8] register read slave address + read ack data[7:0] data[15:8] stop ack data transferred n ( da ta[ 15 :8 ]+ ack+ da ta[7:0] + ack/ nack) master start sr slave address + write register address nack stop slave ack ack data[7:0] register read slave address + read ack data[15:8] ack i 2 c write i 2 c single word read mode i 2 c multiword read mode 12722-012 f igure 19 . i 2 c write and read operations typical connection d iagram figure 21 and figure 22 show two possible photodiode input connections for the adpd103 . the 1.8 v i 2 c communication lines, scl and sda, along with the int line, connect to a system microprocessor or sensor hub. the i 2 c signals can have pull - up resistors connected to a 1.8 v or a 3.3 v power supply. the int and p ds o signals are only compatible with a 1.8 v supply and may need a level translator. provide the 1.8 v supply , v dd , to a vdd and d vdd. use single (v led ) or multiple (v led1 , v led2 , and v led3 ) sources for the led supply using standard regulator circuits according to the peak current requirements specified in table 3 and calculated in the calculating current consumption section. for best noise performance, connect agnd, dgnd (exposed p ad) , and lgnd together at a large conductive surface such as a ground plane, a ground pour, or a large ground trace. the number of photodiodes or le ds used varies . there are multiple ways to connect photodiodes to the input channels , as shown in table 16 and figure 23. the photodio de anodes are connect ed to the pd1 to pd8 input pins, and the photodiode cathodes are connected to the c athode pin. with large photodiodes, the dynamic range can be increased by splitting the current b etween multiple inputs. as a result, i f only one large photodiode is used and the receive s ignal is expected to be large, the di ode can be branched across all four inputs in a given time slot. this type of configuration is shown in figure 21. for si tuations where the photodiode is small or the signal is greatly attenuated, the photodiode can be connecte d directly to a single channel such as pd1 or pd5 . this connection , shown in figure 22 , maximizes snr for low signals . do not connect the same photodiode to all eig ht input channels . it is important to leave the unused input channels floating for proper dev ice operation. the wlcsp package is internally wired for high dynamic range mode. figure 20 shows the recommended connect ion diagram and printed circuit board ( pcb ) layout for the adpd103 wlc sp package. see figure 21 or figure 22 for connection details. the c urrent input pins (pd1 to pd8) have a typical voltage of 1.3 v during the sampling period. during the sleep period , the se pins are connected to the c athode pin. the cathode and anode voltages are listed in table 3 . 1 2 3 a b c d e f lgnd ledx2 ledx3 ledx1 sda scl int dvdd dgnd pdso vref avdd pd5-8 pdc pd1-4 agnd 12722-014 f igure 20 . wlcsp package connection and pcb layout diagram (top view) int pdso dvdd agnd vref avdd pd1 pd2 pd3 pd4 pdc pd5 pd6 pd7 pd8 nic nic nic nic nic nic sda scl lgnd ledx2 ledx3 ledx1 nic 1 7 21 15 28 22 8 14 adpd103 top view (not to scale) 4.7f 4.7f v led2 v led1 4.7f v led3 i 2 c bus to/from host processor power-down control 0.1f 0.1f 0.1f 1.8v 12722-017 f igure 21 . connection diagram for increased dynamic range
adpd103 data sheet rev. b | page 22 of 52 int pdso dvdd agnd vref avdd pd1 pd2 pd3 pd4 pdc pd5 pd6 pd7 pd8 nic nic nic nic nic nic sda scl lgnd ledx2 ledx3 ledx1 nic 1 7 21 15 28 22 8 14 adpd103 top view (not to scale) 4.7f 4.7f v led2 v led1 4.7f v led3 i 2 c bus to/from host processor power-down control 0.1f 0.1f 0.1f 1.8v 12722-013 f igure 22 . conn ection options for individual single channel diodes 12722-020 pdc pd5 pd6 pd7 pd8 7 15 8 14 pd1 pd2 pd3 pd4 pdc 7 15 8 14 pd1 pdc 7 15 8 14 pd1 pd2 pd3 pd4 pdc 7 15 8 14 pd1 pdc pd5 7 15 8 14 pd1 pd8 pd3 pd4 pdc pd5 pd6 7 15 8 14 pd2 pd7 f igure 23 . typical photodiode connection diagram table 16. typical photodiode anode to input channel connections i nput channel photodiode anode confi guration pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 single photodiode ( d1 ) d1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 d1 nc 1 nc 1 nc 1 d1 d1 d1 d1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 d1 d1 d1 d1 two photodiodes ( d1 , d2 ) d1 nc 1 nc 1 nc 1 d2 nc 1 nc 1 nc 1 d1 d1 d1 d1 d2 d2 d2 d2 four photodiodes ( d1 to d4 ) d1 d2 d3 d4 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 d1 d2 d3 d4 eight photodiodes (d1 to d8) d1 d2 d3 d4 d5 d6 d7 d8 1 nc means do not connect under the conditions provided in table 16. leave all unused inputs floating.
data sheet adpd103 rev. b | page 23 of 52 led driver pins and led supply voltage the led x 1, led x 2, and led x 3 pins have an absolute maximum vol tage rating of 3.6 v. any voltage exposure over this rating affects the re liability of the device operation and, in certain circumstances, causes the device to cease proper operation. the voltage of the l edx pins must not be confused with the supply voltages for the led themselves (v ledx ). v ledx is the voltage applied to the ano de of the external led, whereas the ledx pin is the input of the internal current driver, and the pins are connected to the cathode of the external led. led driver operation the led driver for the adpd103 is a current sink requiring 0.2 v of compliance above ground to maintain the programmed current level. figure 24 shows the basic schematic of how the adpd103 connects to an led through the led driver. the determining the average current and the determining c vled sections define the requirements for the bypass capacitor (c vled ) and the supply voltages of the leds (v ledx ). adpd103 ledx lgnd v ledx supply c vled 12722- 1 18 f igure 24 . v ledx supply schematic determining the aver age current t he adpd103 drives an led in a series of short pulses. figure 25 shows the typical adpd103 configuration of a pulse burst sequence. i led_max 3s 19s 12722-119 f igure 25 . typical led pulse burst sequence configuration in this example , the led pulse width, t led_pulse , is 3 s, and the led pulse period, t led_period , is 19 s. the led being driven is a pair of green leds driven to a 250 ma peak. the goal of c vled is to buffer the led between individual pulses. in the worst case scenario, where the pulse train shown in figure 25 is a continuous sequence of short pulses, the v ledx supply must supply the average current. therefore, calculate i led_average as follows: i led_average = ( t led_pulse / t led_period ) i led_peak (1 ) w here: i l e d _ av e r ag e is the average current needed from the v ledx s upply during the puls e period , and it is also the v ledx supply current rating. i led_peak is peak current setting of the led. for the numbers shown in equation 1 , i led_average = 3/19 i led_peak . for typical led timing, the average v ledx supply current is 3/19 250 ma = 39.4 ma, indicating that the v ledx supply must support a dc current of 40 ma. determining c vled to determ ine the c vled capacitor value, determine the maximum forward - bias ed voltage, v fb_led_max , of the led in operation. the led current, i fb_led_max , converts to v fb_led_max as shown in figure 26 . in th is example, 2 50 ma of current thr ough two green leds in parallel yields v fb _led_max = 3.95 v. any series resistance in the led path must also be included in this voltage. when designing the led path, keep in mind that small resistances can add up to large voltage drops due to the led peak current being very large . in addition, these resistances can be unnecessary constraints on the v ledx supply. 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 50 100 150 200 250 led forward-bias voltage drop (v) led driver current setting (ma) two 528nm leds one 850nm led 12722-120 f igure 26 . example of the average led forward - biased voltage drop as a function of the driver current to correctly size the c vled capacitor , do not deplete it during the pulse of the led to the point where the voltage on the cap acitor is less than the forward bias on the led. to calculate the minimum value for the v ledx bypass capacitor, use the following equation : )2.0 ( __ _ __ + ? = is the led pulse width. i fb_led_max is the maximum forward - bias ed current on the led used in operating the device. v led_min is the lowest voltage from the vledx supply with no load. v fb_led_max is the maximum forward - bias ed voltage required on the led to achieve i led_peak .
adpd103 data sheet rev. b | page 24 of 52 the numerator of the c vled equation sets up the total discharge amount in coulombs from the bypass capacitor to satisfy a single programmed led pulse of the maximum current. the denominator represent s the difference between the lowest voltage fr om the v ledx supply and the led required voltage. the led required voltage is the voltage of the anode of the led such that the 0.2 v compliance of the led driver and the forward - bias ed voltage of the led opera ting at the maximum current is satisfied . for a typical adpd103 example, assume that the lowest value for the v ledx supply is 4.4 v, a nd that the peak current is 250 ma for two 528 nm leds in p arallel. the minimum value for c vled is then equal to 3 f. c vled = (3 10 ?6 0.250 )/(4.4 C (3.95 + 0.2)) = 3 f (3 ) as sh own in the e quation 3 , as the minimum supply voltage drops close to the maximum anode voltage , the demands on c vled become more stri ngent , forcing the capacitor value higher. it is important to insert the correct values into these equations. for example, using an average value for v led _ min instead of the worst case value for v led _ min can cause a serious design deficiency , resulting in a c vled value that is too small and that caus es insufficient opt ical power in the application. t herefore, adding a sufficient margin on c vled is strongly recommended. a dd a dditional margin to c vled to account for derating of the capacitor value over voltag e, bias, temperature and other factors over the life of the component. led inductance considera tions the led drivers ( ledx x) on the adpd103 have configurable slew rate settings (register 0x22 , bits [6:4], register 0x23 , bits [6:4], and register 0x 24 , bits [6:4] ). these slew rates are defined in table 3 . even at the lowest setting, careful consideratio n must be taken in board design and layout. if a large se ries inductor , such as a long pcb trace , is placed between th e led cathode and one of the ledx x pin s, voltage spikes from the switched inductor can cause violations of absolute maximum and min imum voltages on the ledx x pins during the slew portion of the l ed pulse . t o v erify t hat t here are no voltage spikes on the ledx x pins due to parasitic inductance, use an oscilloscope on the ledx x pins to monitor the vo ltage during normal operation. any positive spike >3.6 v may damage the device . in addition , a negat ive spike data sheet adpd103 rev. b | page 25 of 52 written to the fifo. note that both time slots can be enabled to use the fifo , but only if their output data rate is the same. output data rate = f sample / n where : f sample is the sampling frequency. n is the averaging factor for each time slot ( n a for time slot a and n b for time slot b). in other words, n a = n b must be true to store data from both time slots in the fifo. data packets are written to the fifo at the output data rate. a data packet for the fifo consists of a complete sample for ea ch enabled time slot. data for each photodiode channel can be stored as either 16 or 32 bits. each time slot can store 2, 4, 8, or 16 bytes of data per sample , depending on the mode and data format. to ensure that data packets are intact, new data is only written to the fifo if there is sufficient space for a complete packet. any new data that arrives when there is not enough space is lost. the fifo continues to store data when sufficient space exists. always read fifo data in complete packets to ensure tha t data packets remain intact. the number of bytes currently stored in the fifo is available in register 0x00, bits [15:8]. a dedicated fifo interrupt is also available and automatically generates when a specified amount of data is written to the fifo. inte rrupt - based method to read data from the fifo usi ng an interrupt - based method , use the following procedure : 1. in p rogram mode , set the configuration of the time slots a s d esired for operation. 2. write register 0x11 with the desired data format for each time sl ot. 3. set fifo_t h resh in register 0x06, bits [13:8] to the interrupt threshold. a good value for this is the number of 16- bit words in a data packet , minus 1. this cause s an interrupt to generate when there is at least one complet e p acket in the fifo. 4. enable the fifo interrupt by writing a 0 to the fifo_ int_mask in register 0x01 , bit 8. also , configure the interrupt pin (int ) by writing the appropriate value to th e b its in register 0x02. 5. enter normal operation mode by setting register 0x10 to 0x 2. 6. when an in terrupt occurs a. t here is no requirement to read the fifo_samples register, because the interrupt is generated only if ther e is one or more full packet s . optionally, the interrupt routine can check for the presence of more than one available packet by readin g this register. b. w rite 1 to the fifo_access_ena bit ( register 0x5f , bi t 0 ) twice in two consecutive write operations. c. r ead a complete packet using one or more multiword accesses using register 0x60. reading the fif o a utomatically frees the space for new sa mples. d. w rite 0 to t he fifo_access_ena bit (register 0x5f, bit 0). the interrupt automatically clear s when enough data is read from the fifo to bring the data level below the threshold. polling method to read data from the fifo in a polling method , use the following procedure : 1. in program mode , set the configuration of the time slots a s d esired for operation. 2. write register 0x11 with the desired data format for each time slot. 3. enter normal operation mode by setting register 0x10 to 2. next, b egin the polling operations. 1. wait for the polling interval to expire. 2. read the fifo _samples bits (register 0x00, b it s [15:8] ). 3 . i f fifo_samples the packet size , read a p acket using the following steps: a. w rite 1 to the fifo_access_ena bit ( register 0x5f , bi t 0 ) twice in two consecutive write operations . b. read a complete packet using one or more multiwor d a ccesses using register 0x60. reading the f if o a utomatically frees the space for new samples. c. wr ite 0 to the fifo_access_ena bit (register 0x5f, bit 0 ). d. repeat s tep 1. when a mode change is required , or any other disruption to normal sampling is necessary, the fifo must be cleared. use the followin g procedure to clear the state and empty the fifo: 1. enter p rogram mode by setting register 0x10 to 0x1. 2. write 1 to the fifo_access_ena bit ( register 0x5f , bi t 0 ) twice in two consecutive write operations. 3. write 1 to register 0x00 , bit 15 . 4. write 0 to the fif o_access_ena bit ( register 0x5f , bit 0). reading data from r egisters u sing interrupts the latest sample data is always available in the data registers and is updated simultaneously at the end of each time slot. the data value for each photodio de channel is available as a 16 - bit value in regis - ter 0x64 through register 0x67 for time s lot a , and register 0x68 through register 0x6b for time s lot b. if allowed to reach their maximum va lue, register 0x64 through register 0x6b clip. if register 0x64 th rough regis ter 0x 6b saturate , t he unsaturated (up to 27 bit s ) values for each channel are available in register 0x70 through register 0x77 for time s lot a a nd register 0x78 through register 0x7f for time s lot b. sample interrupts are available to
adpd103 data sheet rev. b | page 26 of 52 indicate when the re gisters are updated a nd can be read. to use the interrupt for a given time slot, use the following procedure: 1. enable the sample interrupt by writing a 0 to the appropriate bit in register 0x01. to enable the interrupt for time slot a, write 0 to b it 5. to enable the interrupt for time slot b, write 0 to b it 6. either or both interrupts can be set. 2. configure the interrupt pin by writing the appropriate value to the bits in register 0x02. 3. an interrupt generates when the data registers are updated. 4. the interr upt handler must perform the following: a. read register 0 x00 and observe bit 5 or bit 6 to confirm which interrupt has occurred. this step is not required if only one interrupt is in use. b. read the data registers before the next sample can b e w ritten. the sys tem must have interrupt latency and service time short enough to respond before the next data update, based on the output data rate. c. write a 1 to bit 5 or bit 6 in register 0x00 to clear the interrupt. if both time slots are in use , it is possible to use o nly the time s lot b interrupt to signal when all registers can be read. it is recommended to use the multiword read to transfer the data from the data registers. reading data from r egisters w ithout i nterrupts if the system interrupt response is not fast or predictable enough to use the interrupt method, or if the interrupt pin is not used, it is possible to get reliable data access by us ing the data hold mechanism. to guarantee that the data read from the registers is from the same sample time, it is necess ary to prevent the update of samples while reading the current values. the method for doing register reads without interrupt timing is as follows: 1. write a 1 to slota_data_hold or slotb_data_ hold ( register 0x5f , bit 1 and bit 2, respectively ) for the time slot requiring access ( both time slots can be accessed ). this prevents sample updates. 2. read the registers as desired . 3. write a 0 to the slota_data_h old or slotb_data_ hold bits ( register 0x5f , bit 1 and bit 2, respectively ) p reviously set. sample updates are allowed again. because a new sample may arrive while the reads are occurring, this method prevents the new sample from partially overwriting the data being read. clocks and timing ca libration the adpd103 operate s using two internal time bases: a 32 khz clock sets the sample timing, and a 32 mhz clock controls the timing of the internal functions such as led pulsing and data capture. both clocks are internally generated and exhibit device - to - de vice variation of approximately 10% (typical). heart rate monitoring applications require an accurate time base to achieve an accurate count of beats per minute. the adpd103 provides a simple calibration procedure for both clocks. 1. calibrating the 32 khz clock. this calibrates items associa ted with the output data rate. calibration of this clock is important for applications where an accurate data rate is important , such as heart rate measuremen ts. a. set the sampling frequency to the highest the system can handle, such as 2000 hz. because the 32 khz cloc k c ontrols sample timing, its frequency is read ily accessible via the int pin. configure the interrupt by writing the appropriate value to the bits in register 0x02 and set the interrupt to occur at the sampling frequency by writing 0 t o register 0x 0 1, bit 5 or bit 6 . monitor the int pin. t he interrupt frequency must match the set sample frequency . b. i f the monitored interrupt frequency is less than t he set sampling frequency, increase the clk32k_adjust bit (register 0x4b, bits[5:0]). if the monitored interrup t f requency is larger than the set sampling frequency, decrease the clk32k_adjust bits. c. repeat step b unti l the monitored interrupt signa l f requ ency is close enough to the set sampling frequency. 2. calibr ate the 32 mhz clock. this calibrates items associated with the fine timing within a sample period , such as led pulse width and spacing , assuming that the 32 k hz cloc k h as been calibrated. a . wr i te 0x1 to register 0x5f, bit 0 . b. enable the clk_ratio calculation by writing 0x1 to register 0x50, bi t 5 . this function counts the number of 32 mhz clock cycles in two cycles of the 32 khz clock. with this function enabled , this cycle value is stored i n register 0xa, bits [11:0] and nominally this ratio is 2000 (0x7d0). c. c alculate the 32 mhz clock error as follows: clock error = 32 mhz (1 ? clk_ratio /2000) d. adjust the frequency by setting bits[7:0] in register 0x4d per the following equation: clk3 2m_adjust = clock error /109 khz e. wri te 0x0 to register 0x50, bit 5 to reset the clk_ratio function. repeat step 2b through step 2 e until the desired accuracy is achieved. write 0x0 to register 0x5f , bit 0 . also , set the int pin back to the mode desired f or normal operation.
data sheet adpd103 rev. b | page 27 of 52 calculating current consumption the current consumption of the adpd103 depends on the user selected operating configuration, as described in the following equations. total power consumption to calculate the total power consumption, use equation 4. ledb avg ledb leda avg leda dd avg vdd v i v iv i power total + + = _ _ _ (4) average v dd supply current to calculate the average v dd supply current, use equation 5. standby vdd proc slotb b afe s lota a afe avgvdd iq titi dr i _ _ _ _ ) ) () (( ++ += = the data r ate in hz. i vdd _standby = 3.5 10 ?3 ma. proc is an average charge associated with a processing time, as follows: ? only time slot a enabled : proc = 0.64 10 ?3 mc ? only time slot b enabled : proc = 0.51 10 ?3 mc ? time slot a and time slot b enabled : proc = 0.69 10 ?3 mc 225/)25 ( ) _5.1(9.2)ma( _ ? + += count pulse period ledx offset ledx t slotx _ _ _ (sec) + = is the number of active channels . ledx peak is the peak led current expressed in ma . ledx_offset is the pulse start time offset expressed in seconds. ledx_period is the pulse period expressed in secon ds. pulse_count is the number of pulses. note that if either time slot a or time slot b are disabled, i afe_x = 0 for that respective time slot. additionally, if operating in digital integrate mo de , power savings can be realized by setting register 0x3c , bi ts [8:3] = b010010. this setting disables the band - pass filters that are bypassed in digital integ rate mode , changing the afe power contribution calculation to: 225/)25 ( ) _0.1(9.2) ma ( _ ? + += peak x afe ledx channels num i average v leda supply current to calculate the average v leda supply curren t, use equation 8 . i led_avg _a = ( slota_led_width /1 10 6 ) leda peak dr pulse_count (8) where leda peak is led1 peak , led2 peak , or led3 peak , expressed in ma, for whichever led is selected for time slot a. average v ledb supply current to calculate the ave rage v ledb supply current, use equation 9 . i led_avg _b = ( slotb_led_width /1 10 6 ) ledb peak dr pulse_count (9) where ledb peak is led1 peak , led2 peak , or led3 peak , expressed in ma, for whichever led is selected for time slot b. optimizing snr per w att t he adpd103 offers a variety of parameters that the user can adjust to achieve the best signal. one of the key goals of sy s tem performance is to obtain the best system snr for the lowest total p ower. this is often referred to as optimizing snr/ w att . even in systems where only the snr matters and power is a secondar y concern, there may be a lower power or a high power means of achieving the same snr. optimizing for peak snr the first step in optimizing for peak snr is to find a tia gain and led level that gives the best performance where the number o f led pulses remains constant. if peak snr is the goal, the noise section of table 3 can be used as a guide. it is important to note that the snr improve s as a square root of the number of pulses averaged together, wh ereas the increase in the led p ower consumed is directly proportion al to the number of led pulses. in other words , for every doubling of the led pul se count , there is a doubling of the led p ower consumed and a 3 db snr improvement. as a result , avoid any change in the gain configuration that provides less than 3 db of improvement for a 2 power penalty ; any tia gain configuration that provides more th an 3 db of improvement for a 2 p ower penalty is a good choice. i f peak snr is the goal and there is no issue saturating the photodiode with led current at any gain, the 50k tia gain setting is an optimal choice. after the snr per pulse per channel is opti mized , the user can then increase the number of pulses to achieve the desired system snr. optimizing snr per watt in a signal limited system in practice , optimizing for peak snr is not always practical. one scenario in which the photoplethysmography (ppg) signal has a poor snr is the signal limited regime. in this scenario , the led current reaches an upper limit before the desired dc return level is achieved. tuning in this case starts where t he peak snr tuning stops. the starting poin t is nominally a 50k gain , as long as the lowest led current setting of 8 ma do es not saturate the photodiode and the 50k gain provides enough protection against intense back - ground light . in these cases , use a 25k gain as the starting point. the goal of the tuning process i s to bring the dc return signal to a specific adc range , such as 50% or 60%. the adc range
adpd103 data sheet rev. b | page 28 of 52 choice is a function of the margin of headroom needed to prevent saturation as the dc level fluctuates over time. the snr of the ppg waveform is always some percentage of the dc level. if the target level cannot be achieved at the base gain , increase the gain and repeat the procedure. the tuning system may need to place an upper limit on the gain to prevent saturation from ambient signals. tuning the pulse count after the led peak current and tia gain are optimized, increasing the number of pulses per sample increases the snr by the square root of the number of pulses. there are two ways to increase the pulse count. the pulse count registers (register 0x31 , bit s[15:8] , and register 0x36, bits[15:8]) change the number of pulses per internal sample. register 0x15, bits[6:4] and bits[10:8], controls the number of internal samples that are averaged together before the data is sent to the output. therefore, the number of pul ses per sample is the pulse count register multiplied by the number of subsequent samples being averaged. in general, the internal sampling rate increases as the number of internal sample averages increase to maintain the desired output data rate. the snr/ w att is most optimal with pulse count values of 16 or less. above pulse count values of 16, the square root relationship does not hold in the pulse count register. however, this relationship continues to hold when averaged between samples using register 0x 15. note that increasing led peak current increases snr almost directly proportional to led power , whereas increasing the number of pulses by a factor of n results in only a nominal ( n ) increase in snr. when using the sample sum/average function (register 0x15) , the output data rate decreases by the number of summed samples. to maintain a static output data rate, increase the sample frequency (register 0x12) by the same factor as that selected in register 0x15 . for example, for a 100 hz output data rate an d a sample sum/average of four samples, set the sample frequency to 400 hz. single afe channel m ode when using a single photodiode in an application, and that photodiode is connected to a single afe channel (see tab le 16 ), the adpd103 has an option to power down channel 2, channel 3, and channel 4, which places the device in single afe channel mode. because three of the four afe channels are turned off in this mode , the power consumption is considerably reduced. it is important to leave the unused input channels floating for proper device operation. to r un t he device in single afe channel mode , write 0x38 to register 0x3c, bits[8:3]. if it is not require d to run the device in single afe channel mode , leave register 0x3c, bits[8:3] at 0x0 0. tia_adc mode there is a way to put the device in to a mode that effectively runs the tia directly in the adc without using the analog band - pass filter and integrator. t his mode is referred to as tia_adc mode . there are two basic application s of tia_adc mode . in normal operation, all of the background light is blocked from the signal chain, and therefore can not be measured. tia_adc mode can be used to measure the amount o f background/ ambient light. this mode can also be used to measure other dc input currents , such as leakage resistance. when the device is in tia_adc mode , the band - pass filter and the integrator stage are bypassed. this effectively wires the tia directly i nto the adc . at the set sampling frequency, the adc samples channel 1 through channel 4 (or channel 5 through channel 8) in sequential order , and each sample is taken at 1 s intervals . the tia is in an inverting configuration ; therefore, the signal drop s as more light hits the photodiode . zero light or dark conditions result in approximate ly 13,000 lsbs from the adc. to put the adpd103 in tia_adc mode during time slot a , write 0xb065 to registe r 0x43 to bypass the band - pass filter and integrator. similarly, to place the adpd103 in tia_adc mode during time slot b, write 0xb065 to register 0x45 . one way to monitor dc and pulsed signal at the same time is to operate tia_adc mode in one time slot and pul se mode in the other time slot. in tia_adc mode, increasing light level causes a decrease in adc codes because the tia stage is inverting. protecting against tia saturation in normal opera tion one of the reasons to monitor tia_adc mode is to protect against environments that may cause saturation. one concern when operating in high light conditions, especially with larger photodiodes, is that the tia stage may become saturated and the adpd103 continues to communicate data. the resulting saturation i s not typical. the tia, based on its settings, can only handle a certain level of photodiode current. based on the way the adpd103 is configured, if there is a current level from the photodiode that is larger than the tia can handle, the tia output during the led pulse effectively extends the current pulse , making it wider. t he afe timing is then violated because the positive portion of the band - pass filter output extends into the negative section of the integration window. th us, th e photo signal is subtra cted from itself, ca using the output signal to decrease when the effectiv e light signal increases. to measure the response from the tia and verify that this stage is not saturating, place the device in tia_adc mode and slightly modify the timing. specifically, sweep slotx_ afe_ offset until two or three of the four channels reach a minimum value (note that tia is in an inverting configuration). all four channels do not reach this minimum value because, typically, 3 s led pulse widths are used and the adc samples the four channels sequentially at 1 s intervals. this procedure ali gns the adc
data sheet adpd103 rev. b | page 29 of 52 sampling time with the led pulse to measure the total amount of light falling on the photodetector (for example, background light + led pulse). if this minimum value is above 0 lsb, the tia is not saturated. however, take care , because even if the result is not 0 lsb, operating the device near saturation can quickly result in saturation if light conditions change. a safe operating region is typically at ? full scale and lower. use table 17 to determine how the input cod es map to adc levels on a per channel per pulse basis. these codes are not the same as in normal mode because the band - pass filt er and integrator are not unity - gain elements. coarse ambient light measurement using the typical values in table 17 , tia_adc mode can be used to measure or quantify the amount of background or ambient light present on the photodetector. the settings are the same in the method described in the protecting against tia saturation in normal operation section , except the timing used in the normal operating mode is sufficient for this mode. there is no need to sweep afe_ offset . if afe_ offset is in the same place as the normal mode operation, the tia_adc mode does not retu rn the same value , regardless of whether the led is on or off. in tia_ mode, the dark level is a high level near 13,000 lsbs p er channel per pulse (s ee table 17 ). to m e a sure this value , select no pd by writing a 0x0 to register 0x1 4 , bits [11:8] for time slot b or register 0x14 , bits [7:4] for time slot a. this setting internally open s the photodiode connection. this give s a base line lsb value that coinc ides with a zero signal input. after register 0x14 is restored to its normal valu e, while connecting the photodiode to the tia, this tia_adc result can be subtracted from the open photodiode case to yield a background light measurement . use table 17 to translate this measureme nt into an input photocurrent. use t his result for co a rse absolute m easurements only , because it is typically only accurate to within 10% . measuring pcb parasitic input resistance during the process of mounting the adpd103 , un desired resistance can develop on the inputs through assembly errors or debris on the pcb. these resistances can form between the anode and cathode, or between the anode and some other supply or ground. in normal operation, the ambient rejection feature of the adpd103 masks the primary effects of these resistances, making it very difficult to detect them. however, even at 1 m to 10 m, such resistance can impact performanc e significantly through added noise or decreased dynamic range. tia _adc mode can be used to screen for these assembly issues. measuring shunt resistance on the photodiode a shunt resistor across the photodi ode does not generally affect the output level of the device in operation because the effective impedance of the tia is very low. this is especially true if the photodiode is held to 0 v in operation. however, such resistance can add noise to the system, d egrading performance. the best way to detect photodiode leakage, also called photodiode shunt resistance, is to place the device in tia_adc mode in the dark and vary the operation mode cathode voltage. when the cathode is at 1.3 v, this places 0 v across t he photodiode because the anode is always at 1.3 v while in operation. when the cathode is at 1.8 v, this places 0.5 v across the photodiode. using the register settings in table 3 to control the cathode voltage, m easure the tia_adc value at both voltages. next, divide the voltage difference of 0.5 v b y the difference of the adc result after converting it to a current. this result is the approximate shunt r esistance. values greater than 10 m may be difficult to measure, but this method is useful in identifying gross failures. table 17 . analog specifications for tia_adc and digital integrate modes parameter test conditions/comments typ unit tia_adc/digital integrat ion saturation levels values expressed per channel, per sample t ia feedback resistor : 25 k ? 38.32 a 50 k ? 19.16 a 100 k ? 9.58 a 200 k ? 4.79 a tia_adc resolution values expressed per channel, per sample t ia feedback resistor : 25 k ? 2.92 na/lsb 50 k ? 1.5 na/lsb 100 k ? 0.73 na/lsb 200 k ? 0.37 na/lsb output with no input current adc offset (register 0x18 to register 0x21) = 0x0 13000 lsb
adpd103 data sheet rev. b | page 30 of 52 measuring tia input shunt resistance another problem that can occur is for a r esistance to develop between the tia input and anothe r supply or ground on the pcb. these resistances can force the ti a into saturation prematurely. this , in turn , takes away dynamic range from the device in operation and adds a johnson noise component to the input. to measure these resistances , place the device in tia_adc mode in the dark and start by measuring the tia_adc offs et level with the photodiode inputs disconnected ( register 0x14 , bits [11:8] = 0 or register 0x14 , bits [7:4] = 0). from this, subtra ct the value of tia_adc mode with the darkened photodiode connected and convert the difference into a current. if the value is positive, and the adc signal decreased , the resistance is to a voltage higher than 1.3 v, such as v dd . current entering the tia c ause s the output to drop. if the output difference is negative due to an increase of codes at the adc, current is being pulled out of the tia and there is a shunt resistance to a lower potential than 1.3 v, such as ground. dig ital integrate m ode digital in tegrate mode is built into the adpd103 and allows the device to accommodate longer led/afe pulse widths and different types of sensors at the input. the analog integration mode describe d in the afe operation section is ideally suited for applications requiring a large led duty cycle, or applications that require customization of the sampling scheme . digital integrate mode allows the integration function to be performed after the adc in the digital domain. this mode enables the device to handle a much wider range of sensors at the input. in digital integrate mode, the adc performs a conversion every 1 s during the integration window. during the integration window, the di gital engine either adds to or subtracts from the previous sample. t he band - pass filter is bypassed and the integrator is converted to a voltage buffer , allowing the digital engine to perform the integration function. in this mode, after the timing is opti mized , the output of the adc increases as the light level on the photodiode increases . the integration window is a combination of negative and positive windows where the duration of these windows is set by slotx_ afe_width. at the end of the digital integr ation window, the resulting sum is sent to the decimate unit as the sample for that led pulse. there is one sample per time slot for every sample cycle . table 18 lists the registers required for placing the device in digital integ rate mode . there may also be changes need ed in the slotx_ afe_offset registers and fifo configuration register (0x11). to read the final value through the fifo , set the appropriat e values in regis - ter 0x11, bits [4:2] for time slot a , and register 0x11, bit s[8:6] for time slot b. alternat iv ely, the final output is also available through the data registers ; register 0x64, register 0x70 , and register 0x74 for time slot a, and register 0x68, register 0x78 , and register 0x7c for time slot b. to put the adpd103 in to digital integration mode during time slot a, write 0x 1 to register 0x 58 , b it 12 . to put the adpd103 in to digital integration m ode in time slot b, write 0x1 to register 0x 58, b it 13 . the other writes required to switch to digital integration mode are listed in table 18 . when using digital integrate mode , up to two photodiodes can be connected to the adpd103 inputs; one photodiode per pd x input g roup (pd1/ pd 2/ pd 3/ pd 4 or pd5/ pd 6/ pd 7/ pd 8). never connect the same photodiode across the two pd x groups. in d ig ital integrate mode , t here are options to connect the photodiode to all four afe channels (pd1/ pd 2/ pd 3/ pd 4 or pd5/ pd 6/ pd 7/ pd 8) , or just a single afe channel (pd1 or pd5) . when connecting to a single afe channel , write 0x1 to register 0x 54, bit 14 for time slot a, o r, for time slot b, write 0x1 to register 0x 54, bit 15 . when c onnecting to a single afe channel , there is also an option to turn off channel 2, channel 3, and channel 4 (and to save power) by writing 0x7 to register 0x55, bits[15:13]. when connecting to all four channels (pd1/ pd 2/ pd 3/ pd 4 or pd5/pd 6/ pd 7/ pd 8) , write 0x0 (default)to register 0x 54, bit 14 for time slot a, or write 0x0 (default) to register 0x 54, bit 15 for time slot b. ensure that all afe channels are powered up by writing 0x0 to register 0x55, bits[15:13 ]. connecting the s ingle photodiode to a single afe channel offers the best snr performance in cases where signal is limited , whereas connecting the single photodio de to all four afe channels offers the best dynamic range in cases where signal is large. digital integration s ampling modes there are two sampling modes that can be used while the device is in digital integrat ion mode. these modes are s ingle - sample pair m ode and d ouble - sample pair mode. in single- samp le pair mode , there is a single negative sample region and a sin gle positive sample region , shown in figure 29 and figure 30. to us e single-sample pair mode , write 0x1 to register 5a, bit 5 for time slot a , or register 5a, bit 6 for tim e slot b. the negative sample region starts at slotx_ afe_ offset + 9 and its duration (the number of samples taken) is set by slotx_ afe_width. the positive sample region starts at slotx_ afe_offset + 9 + slot x_ afe_width , and its dura tion is also set by slot x_ afe_width. set t he timing such that the negative sample region falls entirely in the flat (dark) portion of the led response , whereas the positive sample region falls in the pulsed region of the led response. placing the led pulse offset , slotx_led_offse t, at the beginning of slotx_ afe_offset + 9 + slotx_ afe_width achieve s this timing. the output is the difference of the signals in the two regions.
data sheet adpd103 rev. b | page 31 of 52 double - sample pair mode is another way to sample. i n this mode, there are two negative sample regions and on e long positive sample region (see figure 27 and figure 28 ). to us e double - sample pair mode , write 0x0 to register 0x 5a, bit 5 for time slot a , or bit 6 for time slot b. th e first negative sample region starts at slotx_ afe_offset + 9 and its duration is set by slotx_ afe_width. the positive sample region starts at slotx_ afe_offset + 9+ slotx_ afe_width and its duration is twice the slotx_ afe_width. after this , there is another negative sample region that starts at slotx_ afe_offset + 9+ 3 slotx_ afe_width , and its duration is slotx_ afe_ width. set t he timing such that both of the negative sample regions fall in the flat (dark) portion of the led response and the positive sample region falls in the pulsed portion of the led response. placing the led pulse offset , slotx_led_offset at the beginning of slotx_ afe_offset + 9 + slotx_ afe_ width achieve s this timing. the output is calculated by summing the response of all the r egions in a negative / positive / negative manner. the double - sample pair mode is useful for cases when the background light is not constant because it has better background rejection , but it a lso uses more power than single - sample pair mode. sample timing modes there are two options for timing the sample regions: gapped mode and continuous mode . in gapped timing mode, there is a space between the negative and pos itive sample regions. the width of this region is specified by slota _afe_foffset for time slot a and slotb _afe_ foffset for time slot b in microseconds . to enable this feature , write 0x1 to register 0x 5a, bit 7 . this bit enable s gapped timing for the time slot (or time slots) that are in digital integrat e mode. this mode is helpful when there are unwanted tran sients in the led response that must be ignored for an accurate output. if there are no concerns about led response transients , select contin uous timing mode . in this mode , there is no space between the negative and positive sample regions. write 0x0 to re gister 0x 5a, bit 7 for continuous timing of the sample regions. both gapped and contin uous sample timing modes can be used with single- sample pair or double -s ample pair mode. some example timing diagrams are shown in figure 27, figure 28, figure 29, and figure 30. background values in digital integrate mode , t he digital integration background value , di_ background , or dark values are also stored and available as output data . this is in addition to the output value during the led pulse , di_o utput , which has the dark value subtracted. di_ background is the sum of the negative region samples. t o i nclude these values in the fifo , set register 0x11, bits[4:2] for time slot a, and register 0x11, bits[8:6] for time slot b. for 16- bit data , set this value to 0x3 ; for 32 - bit data , set this value to 0x0 4. these settings are also available thr ough the data registers ; register 0x65, register 0x71 , and register 0x75 for time slot a , and register 0x69, register 0x79 , and register 0x7d for time slot b. it is recommended that the channel offsets (register 0x18 to register 0x21) be set to 0x1f00 when including th e background values in the fifo in digital integration mode. these channel offsets do not affect the sample values , but do provide more headroom for the b ackground values. saturation detection in digital integrate mode in normal operation , when using the b and - pass filter and the integrator , the adc almost always saturate s before the tia. unlike in normal operation, saturation of the tia or the adc cannot be detected solely by looking at the signal value w here the signal value is the positive sample region m inus the reference region in digital integrate mode. this is because the integrated value does not by itself contain any information indicating if one of the adc conversions during the integration period exceeded the adc output range. as a result , t he real - t ime output may have saturated only for a fraction of the adc conversions within a sample and the final accumulated sum may not reflect this. to detect tia saturation in digital integrat ion mode, both the background values, di_b ackground , and the s ignal v alues , di _output , must be collected. refer to the background values section for the correct settings for register 0x11 that provide these values. for single - sample pair mode, saturation has occurred when ( di_o utput /( min ( led_width , afe_width )) + di_background / afe_width )/ num_pulses > 0x3fff for double - sample pair mode, saturation has occurred when ( di_o utput /( min ( led_width , 2 afe_width )) + di_background / (2 afe_width ) )/ num_pulses > 0x3fff
adpd103 data sheet rev. b | page 32 of 52 slotx_afe_offset + 9 sub sub add led sample 12722-021 f igure 27 . digital integration mode in double -s ample pair mode with continuous sample timing slotx_afe_offset + 9 afe_foffset afe_foffset sub sub add led sample 12722-022 f igure 28 . digital integration mode in double - sample pair mode with gapped sample timing 12722-023 slotx_afe_offset + 9 sub add led sample afe_foffset f igure 29 . digi tal integration mode in single - sample pair mode with gapped sample timing 12722-024 slotx_afe_offset + 9 sub add led sample f igure 30 . digital integration mode in single - sample pair mode with continuous sample timing
data sheet adpd103 rev. b | page 33 of 52 table 18. configuration registers to switch between the normal sample mode, tia_adc mode , and digital integration mode address data bits bit name normal mode value tia_adc mode value digital integration mode value description 0x42 [15: 8] slota_afe_mode 0x1c not applicable 0x1d in normal mod e, this setting configures the integrator block for optimal operation. in digital integration mode, this setting configures the integrator block as a buffer. this setting is not important for tia_adc mode . 0x43 [15:0] slota_afe_cfg 0xada5 0xb065 0xae65 ti me slot a afe connection. 0 xae65 bypasses the band - pass filter. 0 xb065 bypasses the band - pass filter and the integrator. 0x44 [15:8] slotb_afe_mode 0x1c not applicable 0x1d in normal mode, this setting configures the integrator block for optimal operation. in digital integration mode, this setting configures the integrator block as a buffer. this setting is not important for tia_adc mode . 0x45 [15:0] slotb_afe_cfg 0xada5 0xb065 0xae65 time slot b afe connection. 0 xae65 bypasses the ba nd - pass filter. 0 xb065 bypasses the bpf and the integrator. 0x4e [15:0] adc_ timing not applicable not applicable 0x0040 set adc clock to 1 mhz in tia_adc mode . 0x58 13 slotb_digital_int_en 0x0 0x0 0x1 digital integrate mode enable time slot b. 0 : disable. 1 : enable. 12 s lota_digital_int_en 0x0 0x0 0x1 digital integrate mode enable time slot a. 0 : disable. 1 : enable. 0x5a [15:0] dig_int_cfg not applicable not applicable variable configuration of digital integration depends on the use case. this register is ignored for other modes.
adpd103 data sheet rev. b | page 34 of 52 register listing table 19 . numeric register listing 1 hex bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 addr name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 status [15:8] fifo_samples[15:8] 0x0000 r/w [7:0] reserved slotb_ int slota_int reserved [4:0] 0x01 int_ mask [15:8] reserved[15:9] fifo_int_mask 0x00ff r/w [ 7:0] reserved slotb_int_ mask slota_int_ mask reserved[4:0 ] 0x02 int_io_ ctl [15:8] reserved[15:8] 0x0000 r/w [ 7:0] reserved[7:3] int_ena int_drv int_pol 0x06 fifo_ thresh [15:8] reserved[15:14] fifo_thresh[13:8] 0x0000 r/w [ 7:0] reserved[7:0] 0x08 devid [15:8] rev_num[15:8] 0x0416 r [ 7:0] dev_i d[7:0] 0x09 i2cs_id [15:8] address_write_key[15:8] 0x00c8 r/w [7:0] slave_address[7:1] reserved 0x0a clk_ ratio [15:8] reserved [15:12] clk_ratio[11:8] 0x0000 r [ 7:0] clk_ratio[7:0] 0x0d slave_ address _key [15:8] slave_address_key[15:8] 0x000 0 r/w [7:0] slave_address_key[7:0] 0x0f sw_ reset [15:8] reserved[15:8] 0x0000 r/w [ 7:0] reserved[7:1] sw_reset 0x10 mode [15:8] reserved [15:8] 0x0000 r/w [7:0] reserved [7:2] mode[1:0] 0x11 slot_en [15:8] reserved [15:14 ] rdout_m ode fifo_o vrn_ prevent reserved[11:9] slotb_fifo_ mode 0x1000 r/w [7:0] slotb_fifo_mode [7:6] slotb_en slota_fifo_ mode[4:2 ] r eserved slota_en 0x12 fsample [15:8] fsample[15:8] 0x0028 r/w [7:0] fsample[7:0] 0x14 pd_led_ select [15:8] reserved[15:12] slotb_ pd_sel[11:8] 0x0541 r/w [ 7:0] slota_pd_sel[7:4] slotb_led_sel[3:2] slota_led_sel[1:0] 0x15 num_ avg [15:8] reserved slotb_num_avg 0x0600 r/w [ 7:0] reserved slota_num_avg reserved 0x18 slota_ ch1_ offset [15:8] slota_ch1_offset[15:8] 0x2000 r/w [ 7:0] slota_ch1_offset[7:0] 0x19 slota_ ch2_ offset [15:8] slota_ch2_offset[15:8] 0x2000 r/w [ 7:0] slota_ch2_offset[7:0] 0x1a slota_ ch3_ offset [15:8] slota_ch3_offset[15:8] 0x2000 r/w [ 7:0] slota_ch3_offset[7:0] 0x1b slota_ ch4_ offset [15:8] slota_ch4_offset[15:8] 0x2000 r/w [ 7:0] slota_ch4_offset[7:0] 0x1e slotb_ ch1_ offset [15:8] slotb_ch1_offset[15:8] 0x2000 r/w [ 7:0] slotb_ch1_offset[7:0] 0x1f slotb_ ch2_ offset [15:8] slotb_ch2_offset[15:8] 0x2000 r/w [ 7:0] slotb_ch 2_offset[7:0] 0x20 slotb_ ch3_ offset [15:8] slotb_ch3_offset[15:8] 0x2000 r/w [ 7:0] slotb_ch3_offset[7:0] 0x21 slotb_ ch4_ offset [15:8] slotb_ch4_offset[15:8] 0x2000 rw [ 7:0] slotb_ch4_offset[7:0]
data sheet adpd103 rev. b | page 35 of 52 hex bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 addr name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x22 iled3_ coarse [15:8] reserved [15:14] iled3_ scale reserved [12:8] 0x3000 r/w [7:0] reserved iled3_slew[6:4] iled3_coarse[3:0] 0x23 iled1_ coarse [15:8] reserved [15:14] iled1_ scale reserved [12:8] 0x3000 r/w [7:0] reserved iled1_slew[6:4] iled1_coarse[3:0] 0x24 iled2_ coarse [15:8] reserved [15:14] iled2_ scale reserved [12:8] 0x3000 r/w [ 7:0] reserved iled2_slew[6:4] iled2_coarse[3:0] 0x25 iled_ fine [15:8] iled3_fine[15:11] iled2_fine[10:8] 0x 6 30c r/w [7:0] iled2_fine[7:6] reserved iled1_fine[4:0] 0x30 slota_ led_ pulse [ 15:8] reserved [15:13] slota_led_width[12:8] 0x0320 r/w [ 7:0] slota_led_offset[7:0] 0x31 slota_ num - pulses [15:8] slota_led_number[15:8] 0x0818 r/w [ 7:0] slota_led_period[7:0] 0x34 led_ disable [15:8] reserved [15: 1 0] slotb_ led_ dis slota_ led_d is 0x0000 r/w [7:0] reserved [7:0] 0x35 slotb_ led_ pulse [15:8] reserved [15:13] slotb_led_width[12:8] 0x0320 r/w [ 7:0] slotb_led_offset[7:0] 0x36 slotb_ num - pulses [15:8] slotb_led_number[15:8] 0x0818 r/w [ 7:0] slotb_led_period[7:0] 0x38 timing_ cfg [15:8] reserved ext_sync_ ena reserved [ 13:8] 0x000 r/w [ 7:0] reserved [7:0] 0x39 slota_ afe_ window [15:8] slota_afe_width[15:11] slota_afe_offset[10:8] 0x22fc r/w [ 7:0] slota_afe_offset[10:5] slota_afe_foffset[4:0] 0x3b slotb_ afe_ w indow [15:8] slotb_afe_width[15:11] slotb_afe_offset[10:8] 0x22fc r/w [ 7:0] slotb_afe_offset[10:5] slotb_afe_foffset[4:0] 0x3c afe_pwr _cfg1 [15:8] reserved[15:14] reserved[13:11] reserved v_ cathode afe_ power - down 0x3006 r/w [7:0] afe_powerdown[7 :3] reserved[2:0] 0x42 slota_ tia_cfg [15:8] slota_afe_mode[15:8] 0x1c38 r/w [ 7:0] reserved slota_ tia_ ind_en reserved[5:2] (write 0xd) slota_tia_gain[1:0] 0x43 slota_ afe_cfg [15:8] slota_afe_cfg[15:8] 0xada5 r/w [7:0] slota_afe_cfg[7:0] 0 x44 slotb_ tia_cfg [15:8] slotb_afe_mode[15:8] 0x1c38 r/w [ 7:0] reserved slotb_ tia_ ind_en reserved[5:2] (write 0xd) slotb_tia_gain[1:0] 0x45 slotb_ afe_cfg [15:8] slotb_afe_cfg[15:8] 0xada5 r/w [7:0] slotb_afe_cfg[7:0] 0x4b sample_ clk [15:8] reserved[15:8] 0x2612 r/w [7:0] clk32k_en reserved clk32k_adjust[5:0] 0x4d clk32m_ adjust [15:8] reserved[15:8] 0x425e r/w [ 7:0] clk32m_adjust[7:0] 0x4e adc_ clock [15:8] adc_clock [15:8] 0x0060 r/w [7:0] adc_clock [7:0] 0x4f ext_ sync_sel [ 15:8] reserved[15:8] 0x2090 r/w [7:0] reserved pdso_ oe pdso_ie reserved ext_sync_sel [3:2] int_ie reserved
adpd103 data sheet rev. b | page 36 of 52 hex bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 addr name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x50 clk32m_ cal_en [15:8] reserved[15:8] 0x0000 r/w [7:0] reserved pdso_ ctrl clk32m_ cal_en reserved[4:0] 0x54 afe_pwr _cfg2 [15:8] slotb _sin - gle_ ch_ dig_int slota_ single_ ch_dig_ int sleep_v_catho de [13:12] slotb_v_ cathode [11:10] slota_v_cathode [9:8] 0x0020 r/w [7:0] reg54_vcat _ enable reserved[6:0] 0x55 tia_in - dep_ gain [15:8] digint_power[15:13] reserved slotb_tia_gain_4 [11:10] sl otb_tia_gain_3[9:8] 0x0000 r/w [7:0] slotb_tia_gain_2[7:6] slota_tia_gain_4[5:4] slota_tia_gain_3[3:2] slota_tia_gain_2[1:0] 0x58 digital_ int_en [15:8] reserved[15:14] slotb_ digital_ int_en slota_ digital_int_ en reserved[11:8] 0x0000 r/w [7:0] r eserved[7:0] 0x5a dig_int_ cfg [15:8] reserved[15:8] 0x0000 r/w [7:0] dig_int_ gapmode slotb_ dig_int_ sample - mode slota_ dig_int_ sample - mode reserved[4:0] 0x5f data_ac cess_ ctl [15:8] reserved[15:8] 0x0000 r/w [ 7:0] reserved[7:3] slotb_ data_ hold slota_dat a_hold digital_ clock_ena 0x60 fifo_ access [15:8] fifo_data[15:8] 0x0000 r [7:0] fifo_data[7:0] 0x64 slota_ pd1_ 16bit [15:8] slota_ch1_16bit[15:8] 0x0000 r [ 7:0] slota_ch1_16bit[7:0] 0x65 slota_ pd2_ 16bit [15:8] slota_ch2_16 bit[15:8] 0x0000 r [ 7:0] slota_ch2_16bit[7:0] 0x66 slota_ pd3_ 16bit [15:8] slota_ch3_16bit[15:8] 0x0000 r [7:0] slota_ch3_16bit[7:0] 0x67 slota_ pd4_ 16bit [15:8] slota_ch4_16bit[15:8] 0x0000 r [ 7:0] slota_ch4_16bit[7:0] 0x68 slotb_ pd1_ 16bit [15:8] slotb_ch1_16bit[15:8] 0x0000 r [ 7:0] slotb_ch1_16bit[7:0] 0x69 slotb_ pd2_ 16bit [15:8] slotb_ch2_16bit[15:8] 0x0000 r [ 7:0] slotb_ch2_16bit[7:0] 0x6a slotb_ pd3_ 16bit [15:8] slotb_ch3_16bit[15:8] 0x0000 r [ 7:0] slotb_ch3_16bit[7:0] 0x6b slotb_ pd4_ 16bit [15:8] slotb_ch4_16bit[15:8] 0x0000 r [ 7:0] slotb_ch4_16bit[7:0] 0x70 a_pd1_ low [15:8] slota_ch1_low[15:8] 0x0000 r [ 7:0] slota_ch1_low[7:0] 0x71 a_pd2_ low [15:8] slota_ch2_low[15:8] 0x0000 r [7:0] slota_ch 2_low[7:0] 0x72 a_pd3_ low [15:8] slota_ch3_low[15:8] 0x0000 r [ 7:0] slota_ch3_low[7:0] 0x73 a_pd4_ low [15:8] slota_ch4_low[15:8] 0x0000 r [ 7:0] slota_ch4_low[7:0] 0x74 a_pd1_ high [15:8] slota_ch1_high[15:8] 0x0000 r [ 7:0] slota_ch1_hig h[7:0]
data sheet adpd103 rev. b | page 37 of 52 hex bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 addr name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x75 a_pd2_ high [15:8] slota_ch2_high[15:8] 0x0000 r [7:0] slota_ch2_high[7:0] 0x76 a_pd3_ high [15:8] slota_ch3_high[15:8] 0x0000 r [ 7:0] slota_ch3_high[7:0] 0x77 a_pd4_ high [15:8] slota_ch4_high[15:8] 0x0000 r [ 7:0] slota_ch4_h igh[7:0] 0x78 b_pd1_ low [15:8] slotb_ch1_low[15:8] 0x0000 r [ 7:0] slotb_ch1_low[7:0] 0x79 b_pd2_ low [15:8] slotb_ch2_low[15:8] 0x0000 r [ 7:0] slotb_ch2_low[7:0] 0x7a b_pd3_ low [15:8] slotb_ch3_low[15:8] 0x0000 r [ 7:0] slotb_ch3_low[7:0 ] 0x7b b_pd4_ low [15:8] slotb_ch4_low[15:8] 0x0000 r [ 7:0] slotb_ch4_low[7:0] 0x7c b_pd1_ high [15:8] slotb_ch1_high[15:8] 0x0000 r [7:0] slotb_ch1_high[7:0] 0x7d b_pd2_ high [15:8] slotb_ch2_high[15:8] 0x0000 r [ 7:0] slotb_ch2_high[7:0] 0x7e b_pd3_ high [15:8] slotb_ch3_high[15:8] 0x0000 r [7:0] slotb_ch3_high[7:0] 0x7f b_pd4_ high [15:8] slotb_ch4_high[15:8] 0x0000 r [ 7:0] slotb_ch4_high[7:0] 1 recommended values not shown. only power - on reset values are in table 19 . the recommended values are largely dependent on use case. see table 20 to table 26 for the recommended values.
adpd103 data sheet rev. b | page 38 of 52 led control register s table 20 . le d control registers address data bit default value access name description 0x14 [15:1 2] 0x0 r/w reserved write 0x0 to these bits for proper operation. [ 11:8] 0x5 r/w slotb_pd_sel pdx connection selection for time slot b . see fi gure 13 . 0x1: all photodiode inputs are connected during time slot b. 0x 4: pd5/ pd6/ pd7/ pd 8 are connected during time slot b. 0x5: pd1/ pd 2/ pd 3/ pd 4 are connected during time slot b. o ther: reserved. [7:4] 0x4 r/w slota_pd_sel pd x connection selection for time slot a . see figure 13 . 0x 1: all photodiode inputs are connected during time slot a. 0 x4: pd5/pd6/pd7/pd8 are connected during time slot a. 0x5: pd1/ pd 2/ pd 3/ pd 4 are connected durin g time slot a. o ther: reserved. [ 3:2] 0x0 r/w slotb_led_sel time slot b led configuration . these bits determine which led is associated with time slot b. 0x0: reserved. 0x 1: led x 1 pulses during time slot b. 0x 2: led x 2 pulses duri ng time slot b. 0x3: led x 3 pulses during time slot b. [1:0] 0x1 r/w slota_led_sel time slot a led configuration . these bits determine which led is associated with time slot a. 0 x0: reserved. 0x1: led x 1 pulses during time slot a. 0x 2: led x 2 pulses during time slot a. 0x3: led x 3 pulses during time slot a. 0x22 [15:14] 0x0 r/w reserved write 0x0. 13 0x 1 r/w iled3_scale led x 3 current scale factor. 1: 100% strength. 0 : 40% strength; sets the led x 3 driver in low power mode. le d x 3 current scale = 0.4 + 0.6 ( register 0x22 , bit 13 ). 12 0x 1 r/w reserved write 0x1. [ 11:7 ] 0x0 r/w reserved write 0x0 . [ 6:4] 0x0 r/w iled3_slew ledx3 driver slew rate control. the slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the led driver. 0: the slowest slew rate. 7 : the fastest slew rate. [ 3:0] 0x0 r/w iled3_coarse ledx3 coarse current setting. coarse current sink target value of ledx3 in standard opera tion. 0: 25 ma. 1: 40 ma. 2: 55 ma. 15: 250 ma. l ed3 peak = led3 coarse led3 fine led3 scale w here: led3 peak is the ledx3 peak target value (ma). led3 coarse = 28 + 15.46 ( register 0x22 , bits[ 3:0]). led3 fine = 0.71 + 0.024 ( register 0x25 , bits [15:11]). led3 scale = 0.4 + 0.6 ( register 0x22 , bit 13 ).
data sheet adpd103 rev. b | page 39 of 52 address data bit default value access name description 0x23 [15:14] 0x0 r/w reserved write 0x0. 13 0x 1 r/w iled1_scale ledx1 current scale factor. 1: 100% strength. 0: 40% str ength; sets the ledx1 driver in low power mode. le dx1 current scale = 0.4 + 0.6 ( register 0x23, bit 13 ). 12 0x 1 r/w reserved write 0x1. [ 11:7] 0x0 r/w reserved write 0x0. [6:4] 0x0 r/w iled1_slew ledx1 driver slew rate control . the slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the led driver. 0 : the slowest slew rate. 7 : the fastest slew rate. [ 3:0] 0x0 r/w iled1_coarse ledx1 coarse current setting . coarse current sink t arget value of ledx1 in standard operation. 0: 25 ma. 1: 40 ma. 2: 55 ma. 15: 250 ma. led1 peak = led1 coarse led1 fine led1 scale w here: led1 peak is the ledx1 peak target value (ma). led1 coarse = 28 + 15 .46 ( register 0x23 , bits [3:0]). led1 fine = 0.71 + 0.024 ( register 0x25 , bits [4:0]). led1 scale = 0.4 + 0.6 ( register 0x23 , bit 13 ). 0x24 [15:14] 0x0 r/w reserved write 0x0. 13 0x 1 r/w iled2_scale ledx2 current scale factor. 1: 100% strength. 0 : 40% strength; sets the ledx2 driver in low power mode. led2 current scale = 0.4 0.6 ( register 0x24, bit 13 ) 12 0x 1 rw reserved write 0x1. [ 11:7] 0x0 rw reserved write 0x0. [ 6:4] 0x0 rw iled2_slew ledx2 driver slew rate control. the slo wer the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the led driver. 0 : the slowest slew rate. 7: the fastest slew rate. [3:0] 0x0 rw iled2_coarse ledx2 coarse curr ent setting. coarse current sink target value of led2 in standard operation. see register 0x23, bits[3:0] for values. l ed2 peak = led2 coarse led2 fine led2 scale w here: led2 peak is the ledx2 peak target value (ma). led2 coarse = 28 + 15.46 ( register 0x24 , bits [3:0]). led2 fine = 0.71 + 0.024 ( register 0x25 , bits [10:6]). led2 scale = 0.4 + 0.6 ( register 0x24 , bit 13 ).
adpd103 data sheet rev. b | page 40 of 52 address data bit default value access name description 0x25 [15:11] 0xc r/w iled3_fine ledx3 fine adjust . current adjust multiplier for led3. l edx 3 fine adjust = 0.71 + 0.024 ( register 0x25 , bits [15:11] ). s ee register 0x22, bits[3:0], for the full led3 formula. [ 10:6] 0xc r/w iled2_fine ledx2 fine adjust. current adjust multiplier for led2. l edx2 fine adjust = 0.71 + 0.024 ( registe r 0x25 , bits [10:6] ). s ee register 0x24, bits[3:0], for the full led2 formula. 5 0x 0 r/w reserved write 0x0. [ 4:0] 0xc r/w iled1_fine ledx1 fine adjust. current adjust multiplier for led1. ledx1 fine adjust = 0.71 0.024 ( register 0x25 , b its [4:0] ) . s ee register 0x23, bits[3:0], for the full led1 formula. 0x30 [15:13] 0x0 rw reserved write 0x0. [ 12:8] 0x3 rw slota_led_width led pulse width (in 1 s step) for time slot a. [7:0] 0x20 rw slota_led_offset led offset width (in 1 s step) for time slot a. 0x31 [15:8] 0x08 rw sl ota_led_number led time slot a pulse count . n a : number of led pulses in time slot a. this is typicall y led1. adjust in the application. a setting of six pulses (0x06) is typical. [ 7:0] 0x18 rw slota_led_period led time slot a pulse period (in 1 s step ). 0x34 [15:10] 0x00 rw reserved write 0x0. 9 0x0 rw slotb_led_dis ti me slot b led disable . 1: di sables t he led assigned to time slot b. register 0x34 keeps the drivers active and prevents them from pulsing current to the leds. disabling both leds via this register is often used to measure the dark level. use register 0x11 instead to enabl e or disable the actual time slot usage and not only the led. 8 0x 0 rw slota_led_dis tim e slot a led disable . 1: disables the led assigned to time slot a. us e register 0x11 instead to enable or disable the actual time slot usage and not only the l ed. [ 7:0] 0x00 rw reserved write 0x00. 0x35 [15:13] 0x0 rw reserved write 0x0. [ 12:8] 0x3 s lotb_led_width led pulse width (in 1 s step ) for time slot b. [ 7:0] 0x20 sl otb_led_offset led offset width (in 1 s step ) for time slot b. 0x36 [15:8] 0 x08 rw slotb_ led_number le d time slot b pulse count . n b : number of led pulses in time slot b. t his is typically led2. a setting of six pulses (0x06) is typical. [ 7:0] 0x18 rw slotb_led_period led time slot b pulse period (in 1 s step ). 0x3 c [15: 14 ] 0 x0 rw reserved write 0x 0 . [ 13:11] 0x6 rw reserved write 0x6 . 10 0x 0 r w reserved write 0x0. 9 0x 0 r w v_cathode 0x0: 1.3 v ( identical to anode voltag e) recommended setting. 0 x1: 1.8 v (reverse bias photodiode by 550 mv t his setting may add noise) . [ 8:3] 0x0 rw afe_powerdown afe channels power - down select . 0 x38: powers down afe channel 2, channel 3, and channel 4. 0 x0: keeps all channels on. [ 2:0] 0x6 rw reserved write 0x6 .
data sheet adpd103 rev. b | page 41 of 52 afe configuration re gisters table 21 . afe global configuration registers address data bit default value access name description 0x3c [15:14] 0x0 r/w reserved write 0x0 . [ 13:11] 0x6 r/w reserved write 0x6 . 10 0x 0 r/w reserved write 0x0. 9 0x 0 r/ w v_cathode 0x0: 1.3 v ( identical to anode voltage ); recommended setting . 0 x1: 1.8 v (reverse bias photodiode by 550 mv. this setting may add noise). [8:3] 0x0 r/w afe_powerdown afe channels power - down select . 0 x38: powers down afe channel 2, channel 3, and channe l 4. 0 x0: keeps all channels on. [ 2:0] 0x6 r/w reserved write 0x6 . 0x54 15 0x0 r/w slo t b_single_ch_dig_int 0: in time slot b, use all four photodiode channels in parallel for digital integration (default setting for highest dynamic range) 1 : in time slot b, u se only channel 1 for digital integration. this li mits connection to pd1 or pd5. 14 0x 0 r/w slo t a_single_ch_dig_int 0: in time slot a, use all four photodiode channels in parallel for digital integration (default setting for highest dy namic range) 1: in time slot a, u se only c han nel 1 for digital integration. this limits connection to pd1 or pd5. 13: 12 0x0 r/w sleep_v_cathode if bit 7 1 this setting is applied to the cathode voltage while the device is in sleep mode. the an ode voltage is always set to the cathode voltage in sleep mode. 0x 0: v dd (1.8 v). 0x 1: 1.3 v. 0x2: 1.55 v. 0x 3: 0.0 v. 1 1:10 0x0 r/w slotb_v_cathode if bit 7 1 this setting is applied to the cathode voltage while the device is in time slot b operation. the anode voltage is always 1.3 v in time slot b mode. 0x 0: v dd (1.8 v). 0x 1: 1.3 v. 0x 2: 1.55 v. 0 x3: 0.0 v (this forward biases a diode at the input). 9: 8 0x0 r/w slota_v_cathode if bit 7 1 thi s setting is applied to the cathode voltage while the device is in time slot a operation. the anode voltage is always 1.3 v in time slot a mode. 0x 0: vdd (1.8 v) . 0x1: 1.3 v . 0x 2: 1.55 v . 0 x3: 0.0 v (this forward biases a diode at t he input) . 7 0x0 r/w reg54_ v cat_enable 0: use the cathode voltage settings defined by register 0x3c , bit 9. 1 : override register 0x3c, bit 9 with cathode settings defined by register 0x54, bits13:8 . 6:0 0x20 r/w reserved write 0x20.
adpd103 data sheet rev. b | page 42 of 52 address data bit default value access name description 0x58 [15:14] 0x0 r/w reserved write 0x0. 13 0x0 r/ w slotb_digital_int_en 0x0: time slot b operating in normal mode. 0x1: time slot b operating in digital integration mode . 12 0x0 r/ w slota_digital_int_en 0x0: time slot a operating in normal mode. 0 x1: time slot a operating in digital integration mode . [11 :0 ] 0x00 0 r/w reserved write 0x000. 0x5a [15:8] 0x0 0 r/w reserved write 0x0 0 . 7 0x0 r/ w dig_int_gapmode digital integrate gapped mode enable. 0: n o gap between negative and positive sampl e regions. 1: use slota_afe_foffset for time slot a or slotb_afe_ f offset for time slot b to specify the gap in s. 6 0x0 r/ w slotb_dig_int_sample_mode digital integrate single sample pair mode for time slot b. 0: double sample pair mode. 1: s ingle sampled pair mode. 5 0x0 r/ w slota_dig_int_sample_mode dig ital integrate single sample pair mode for time slot a. 0: d ouble sample pair mode. 1: single sampled pair mode. [4:0] 0x0 0 r/w reserved write 0x0 0 . ta ble 22 . afe configuration registers, time slot a address data bi t default value access name description 0x39 [15:11 ] 0x4 r/w slota_afe_width afe integration window width (in 1 s step ) for time slot a. [10: 5] 0x17 r/w slota_afe_offset afe i ntegration window coarse offset (in 1 s step ) for time slot a. [4:0] 0x1c r/w slota_afe_ f offset afe integration window fine offset (in 31.25 ns step ) for time slot a. 0x42 [ 15 :8] 0x1c r/w slota_ afe_ mode 0x1c: time slot a afe setting fo r normal mode. all four blocks of the signal chain are in use during normal mode (the tia, the bpf, followed by the integrator (int), and finally the adc). 0x1d : time slot a afe setting for digi tal integrate mode. 7 0x0 r/ w reserved w ri t e 0x0. 6 0x0 r/ w slota_tia_ind_en enable time slot a tia gain individual settings . when it is enabled, the channel 1 tia gain is set via register 0x42 , bits[1:0], and the c hannel 2 through channel 4 tia gain is set via register 0x55 , bits [5:0]. 0: d isable tia gain individual setting. 1 : ena ble tia gain individual setting. [5: 2] 0xe r/w reserved reserved . write 0xd . [1: 0] 0x0 r/w slota_tia_gain transimpedance amplifier gain for time slot a . when slota _tia_ind_en i s enable d , this value is for time slo t b , c hannel 1 tia gain. when slota _tia_ind_en is d isabled, it is for all four time slo t a channel tia gain setting s. 0: 200 k ?. 1: 100 k?. 2: 50 k ?. 3: 25 k ?.
data sheet adpd103 rev. b | page 43 of 52 address data bi t default value access name description 0x43 [15:0] 0xada5 r/w slota_afe_ cfg afe connection in time slot a. 0x ada5: analog full path mode (tia_bpf_int_adc). 0xb065: tia_adc mode. 0xa e65: d igital i ntegration mode. ot hers: reserved. 0x55 [15:13] 0x0 r/w digint_power power - down for channel 2, channel 3, and channel 4 in digital integration mode . 0: k eep all channels powered up. 7: power s down channel 2, channel 3, and channel 4. 12 0x0 r/ w reserved write 0x0 . [1 1:10] 0x0 r/w slotb_tia_gain_4 tia gain for time slot b, channel 4 (pd4). 0: 200 k? 1: 100 k ?. 2: 50 k ?. 3: 25 k?. [9: 8] 0x0 r/w slotb_tia_gain_3 tia gain for time slot b, channel 3 (pd3). 0: 200 k? 1: 100 k ?. 2: 50 k?. 3: 25 k ?. [7: 6] 0x0 r/w slotb_tia_gain_2 tia gain for time slot b, channel 2 (pd2). 0: 200 k ? 1: 100 k?. 2: 50 k ?. 3: 25 k ?. [5: 4] 0x0 r/w slota_tia_gain_4 tia gain for time slot a, channel 4 (pd4). 0: 200 k? 1: 100 k ?. 2: 50 k?. 3: 25 k ?. [3:2] 0x0 r/w slo ta_tia_gain_3 tia gain for time slot a, channel 3 (pd3). 0: 200 k ? 1: 100 k?. 2: 50 k?. 3: 25 k ?. [1: 0] 0x0 r/w slota_tia_gain_2 tia gain for time slot a, channel 2 (pd2). 0: 200 k ? 1: 100 k ?. 2: 50 k ?. 3: 25 k?.
adpd103 data sheet rev. b | page 44 of 52 address data bi t default value access name description 0x5a [15:8] 0x0 r/w reserved write 0x0 . 7 0x0 r/ w dig_int_gapmode digital integration gapped mode enable. 0: n o gap between negative and positive sample regions. 1: use slota_afe_ f offse t for time slot a or slotb_afe_ f offset for time slot b to specify the gap in s. 6 0x0 r/w slotb_dig_int_samplemode digital integration single - sample pair mode for time slot b . 0: do uble sample pair mode. 1: si ngle - sampled pair mode. 5 0x0 r/ w slota_dig_int_samplemode digital integr ation single - sample pair mode for time slot a. 0: double sample pair mode. 1: si ngle - sampled pair mode. [4: 0] 0x0 r/w reserved write 0x0 . ta ble 23 . afe configuration registers, time slot b address data bit default v alue access name description 0x3b [15:11] 0x4 r/w slotb_afe_width afe integration window width ( in 1 s step ) for time slot b. [10: 5] 0x17 r/w slotb_afe_offset afe integration window coarse offset (in 1 s step ) for time slot b. [4: 0] 0x1c r/w slotb_afe_ f offset afe integration window fine offset (in 31.25 ns step) for time slot b. 0x44 [15:8] 0x1c r/w slotb_afe_mode 0x1c: time slot b afe setting for normal mode (tia_bpf_int_adc) . 0x1d: time slot b afe setting for digital integrate mode. 7 0x0 r/ w reserved write 0x0 . 6 0x0 r/w slotb_tia_ind_en enable time slot b tia gain individual settings . when it is enabled, the channel 1 tia gain is set via register 0x4 4 , bits1:0, and the channel 2 through channel 4 tia gain is set via register 0x55, bits 11:6 . 0: d isable tia gain individual setting. 1: en able tia gain individual setting . 5: 2 0xe r/w reserved write 0xd . 1: 0 0x0 r/w slot b _tia_gain transimpedance amplifier gain for time slot b . when slot b _tia_ind_en is enabled, this value is for time slot b, channel 1 tia gain. when slot b _tia_ind_en is disabled, it is for all four time slot b channel tia gain settings. 0: 200 k . 1: 100 k . 2: 50 k . 3: 25 k . 0x45 15:0 0xada5 r/w slotb_afe_ cfg afe connection in time slot b. 0x ada5: analog full path mode (tia_bpf_int_adc). 0xb 065: tia_adc mode. 0x ae65: digital integration mode. others: reserved.
data sheet adpd103 rev. b | page 45 of 52 address data bit default v alue access name description 0x58 [15:14] 0x0 r/w reserved write 0x0. 13 0x0 r/ w dig_int_en_b digital integration mode , enable time slot b. 0: disable. 1: en able. 12 0x0 r/ w dig_int_en_a digital integration mode , enable time slot a. 0: d i sable. 1: en able. [1 1:0] 0x0000 r/w reserved write 0x0000.
adpd103 data sheet rev. b | page 46 of 52 system registers table 24. system registers address data bit default access name description 0x00 [15:8] 0x00 r/w fifo_samples fifo status. number of available b ytes to be read from the fifo. when comparing this to the fifo length threshold (register 0x06, bits[13:8]), note that the fifo status value is in bytes and the fifo length threshold is in words, where one word = two bytes. wi th the fifo_access_ena b it set, write 1 to bit 15 of fifo_samples t o clear the contents of the fifo. 7 0x0 r/w reserved write 0x 1 to clear this bit to 0x0 . 6 0x0 r/ w slotb_int time slot b interrupt. describes the type of interrupt event. a 1 indicates an interrupt of a partic ular event type has occurred. write a 1 to clear the corresponding interrupt. after clearing , the register go es to 0. writing a 0 to this register has no effect . 5 0x 0 r/w slota_int time s lot a interrupt. describes the type of interrupt event. a 1 indica te s an interrupt of a particular event type has occurred. write a 1 to clear the corresponding interrupt . after clearing , the register go es to 0. writing a 0 to this register has no effect [4: 0] 0x00 r/w reserved write 0x1f to clear these bits to 0x00 . 0x01 [15:9] 0x00 r/w reserved write 0x00. 8 0x 0 r/w f ifo_int_mask sends an interrupt when the fifo data length has exceeded the fifo length threshold in register 0x06, bits[13:8]. a 0 enables the interrupt. 7 0x 1 r/w r eserved write 0x 1. 6 0x 1 r/w s lo tb_int_mask sends an interrupt on the time slot b sample . write a 1 to disable the interrupt. write a 0 to enable the interrupt. 5 0x 1 r/w s lota_int_mask sends an interrupt on the time slot a sample. write a 1 to disable the interrupt. write a 0 to enable the interrupt. [4: 0] 0x 1f r/w reserved write 0x 1 f. 0x02 [15:3] 0x0000 r/w reserved write 0x0000. 2 0x0 r/ w int_ena int pin enable. 0: d isable the int pin. the int pin floats regardless of interrupt status. the status register (address 0x00) r emains active. 1: en able the int pin. 1 0x0 r/ w int_drv int drive. 0: t he int pin is always driven. 1: t he int pin is driven when the interrupt is asserted; otherwise, it is left floating and requires a pull - up or pull- down resistor, d ependin g on polarity (operates as open drain). use this setting if multiple devices need to share the int pin. 0 0x0 r/w int_pol int polarity. 0: t he int pin is active high. 1: t he int pin is active low. 0x06 [15:14] 0x0 r/w reserved write 0 x0. [13: 8] 0x00 r/w fifo_thresh fifo length threshold. an interrupt is ge nerated when the number of data - words in the fifo exceeds the value in fifo_thresh. the interrup t pin automatically de asserts when the number of data - words available in the fifo no longer exceeds the value in fifo_thresh. [7: 0] 0x00 r/w reserved write 0x00. 0x08 [15: 8] 0x04 r rev_num revision number . [7: 0] 0x16 r dev_id device id.
data sheet adpd103 rev. b | page 47 of 52 address data bit default access name description 0x09 [15:8] 0x0 w address_write_key write 0 xad when writing to slave_address. otherwise , do not ac cess. [7: 1] 0x64 r/w slave_address i 2 c s lave address . 0 0x0 r reserved do not access . 0x0a [15:12] 0x0 r reserved reserved. read only . [1 1:0] 0x000 r clk_ratio when the clk32m_cal_en bit (register 0x50, bit 5) is set, the device calculates the numbe r of 32 mhz clock cycles in two cycles of the 32 khz clock. the result, nominally 2000 (0x07d0), is stored in the clk_ratio bits. 0x0d [15:0] 0x0 r/w slave_address_key enable changing the i 2 c address using register 0x 0 9. 0x0 4ad: enable address chang e always. 0x4 4ad: enable address change if int is high. 0x8 4ad: enable address change if pdso is high. 0xc 4ad: enable address change if both int and pdso are high. 0x0f [15:1] 0x0000 r reserved reserved. read only . 0 0x0 r/w sw_reset software reset. write 0x1 to reset the device . this bit clear s itself after a reset. this command does not return an acknowledge because the command is instantaneous. 0x10 [15:2] 0x000 r/w reserved write 0x000. [1: 0] 0x0 r/w mode determines the operatin g mode of t he adpd103 . 0x0: standby. 0x 1: program. 0x 2: normal operation. 0x11 [15:1 4 ] 0x0 r/w reserved write 0x0. 13 0x0 r/ w rdout_mode readback data mode for extended da ta registers 0x0: block sum of n samples 0x1: block average of n samples 12 0x1 r/ w fifo_ovrn_prevent 0x0: wrap around fifo, overwriting old data with new. 0x1: new data if fifo is not full (recommended setting). [1 1:9] 0x0 r/w reserved write 0x0 . [8: 6] 0x0 r/w slotb_fifo_mode time slot b fifo data format. 0: no data to fifo. 1: 16 - bit sample in digital integration mode or 16 - bit sum of all 4 channels when not in digital integration mode. 2: 32 - bit sample in digital integratio n mode or 32 - bit sum of all 4 channels when not in digital integration mode. 3: 16 - bit sample and 16 - bit background value in digital integration mode 4: 32 - bit sample and 32 - bit background value in digital integration mode or 4 channels of 16 -b it sample data for time slot b when not in digital integration mode. 6: 4 c hannels of 32 - bit extended sample data for time slot b when not in digital integration mode. ot hers: reserved. th e selected time slot b data is saved in the fifo. available only if time slot a has the same averaging factor, n (register 0x15, bits[10:8] = bits[6:4]), or if time slot a is not saving data to the fifo (register 0x11, bits[ 4 :2] = 0). 5 0x0 r/ w slotb_en time slot b enable. 1: enables time slot b.
adpd103 data sheet rev. b | page 48 of 52 address data bit default access name description [4 :2] 0x 0 r/w slota_fifo_mode time slot a fifo data format. 0: no data to fifo. 1: 16 - bit sample in digital integration mode or 16 - bit sum of all 4 channels when not in digital integration mode. 2: 32 - bit sample in digital integration mod e or 32 - bit sum of all 4 channels when not in digital integration mode. 3: 16 - b it sample and 16 - bit background value in digital integration mode 4: 32 - bit sample and 32 - bit background value in digital integration mode or 4 channels of 16 - bit sa mple data for time slot b when not in digital integration mode. 6: 4 channels of 32 - bit extended sample data for time slot b when not in digital integration mode. ot hers: reserved. 1 0x0 r/ w reserved write 0x0 . 0 0x0 r/ w slota_en time slot a enable. 1: enables time slot a. 0x38 15 0x0 r/w reserved write 0x0 . 14 0x0 r/ w ext_sync_ena enables external sampling trigger . 0x 0: samples triggered internally. 0x 1: samples triggered externally. must be set to 1 if ext_sync_sel is b01 o r b10. [13: 0] 0x0 r/w reserved write 0x0 . 0x4b [15: 9 ] 0 x13 r/w reserved write 0x 1 3 . 8 0x0 r/ w clk32k_byp bypass internal 32 khz clock oscillator . 0x0: normal operation . 0x1 : use an external clock on the pdso pin . 7 0x0 r/ w clk32k_en samp le clock power - up. enables the data sample clock. 0x0: clock disabled. 0x 1: normal operation. 6 0x0 r/ w reserved write 0x0. [5: 0] 0x12 r/w clk32k_adjust data sampling (32 khz) clock frequency adjust. this register is used to calibrate the s ample frequency of the device to achieve high precision on the data rate as defined in register 0x12. adjusts the sample master 32 khz clock by 0.6 khz per lsb. for a 100 hz sample rate as defined in register 0x12, 1 lsb of register 0x4b, bits[5:0], is 1.9 hz. no te that a larger value produces a lower frequency. see the clocks and timing calibration section for more information regarding clock adjustment. 00 0000: maximum frequency. 10 0010: typical center freque ncy. 11 1111: minimum frequency. 0x4d [15:8] 0x42 r/w reserved write 0x42. [7: 0] 0x5e r/w clk32m_adjust internal timing (32 mhz) clock frequency adjust. this register is used to calibrate the internal clock of the device to achieve precisely timed led pulses. adjusts the 32 mhz clock by 109 khz per lsb. see t he clocks and timing calibration section for more information regarding clock adjustment. 00 00 0000: minimum frequency. 0101 1110: default frequency . 11 11 1111: maximum frequency. 0x4e 1 [15:0] 0x0060 r/w adc_ timing 1 0x0040 : adc clock speed = 1 mhz . 0x00 60: adc clock speed = 500 khz.
data sheet adpd103 rev. b | page 49 of 52 address data bit default access name description 0x4f [15:7] 0x41 r/w reserved write 0x41 . 6 0x0 r/ w pdso_oe pdso pin output enable . 5 0x0 r/ w pdso_ie pdso pin input enable . 4 0x1 r/ w reserved write 0x1 . [3: 2] 0x0 r/w ext_sync_sel sample sync select . 00: us e the internal 32 khz clock with fsample to select sample timings . 01: us e the int pin to trigger sample cycle . 10: us e the pds o pin to trigger sample cycle . 11: reserved. 1 0x0 r/ w int_ie int pin input enable . 0 0x0 r/w reserved write 0x0. 0x50 [15:7 ] 0x000 r/w reserved write 0x000. 6 0x0 r/ w pdso_ctrl controls the pdso output when the pdso output is enabled (pdso_oe = 0x1). 0x0 : pdso output driven low . 0x1: pdso output driven by the afe power - down signal . 5 0x0 r/ w clk32m_cal_en as part of the 32 mhz clock calibration routine, write 1 to begin the clock ratio calculation. read the result of this calcula tion from the clk_ratio bits in register 0x0a. res et this bit to 0 prior to reinitiating the calculation. [4:0] 0x0 r/w reserved write 0x0. 0x5f [15:3] 0x0000 r/w reserved write 0x0000. 2 0x0 r/ w slotb_data_hold setting this bit prevents the up date of the data registers corresponding to time slot b. set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: h old data registers for time slot b. 0: all ow data register update. 1 0x0 r/ w slota_data_hold setting this bit prevents the update of the data registers corresponding to time slot a. set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: h old data registers for time slot a. 0: allow data register update. 0 0x0 r/ w fifo_access_ena set to 1 twice to enable fifo access. it is necessary to write 1 to the fifo_access_ena bit in two consecutive write operations in order to read data from the fifo. during clock calibration, set to 1 to force the 32 mhz clock to run. for power savings, reset to 0 when the previously described operations are complete. 1 clock speed setting is only relevant during digital integrate mode.
adpd103 data sheet rev. b | page 50 of 52 adc registers table 25 . adc registers address data bits default access name description 0x12 [15:0] 0x0028 r/w fsample sampling frequency: f sample = 32 khz /( register 0x12 , bits [15:0] 4). f or example, 100 hz = 0x0050; 200 hz = 0x0028. 0x15 [15:11] 0x0 r/w reserved write 0x0 . [10:8] 0x6 r/w slotb_num_avg sample sum/average for time slot b. specifies the averaging factor, n b , which is the number of consecutive samples that is summed and averaged aft er the adc. register 0x70 to register 0x7f hold the data sum. register 0x64 to register 0x6b and the data buffer in register 0x60 hold the data average, which can be used to increase snr without clipping, in 16 - bit registers. the data rate is decimated by the value of the slotb_numb_avg bits. 0: 1 . 1: 2 . 2: 4 . 3: 8 . 4: 16 . 5: 32 . 6: 64 . 7: 128 . 7 0x 0 r/w reserved write 0x0. [ 6:4] 0x0 r/w slota_num_avg sample sum/average for time slot a. n a : same as bits[10:8] but for time slot a. see description in register 0x15, bits[10:8]. [ 3:0] 0x0 r/w reserved write 0x0. 0x18 [15:0] 0x2000 r/w slota_ch1_offset time slot a channel 1 adc offset. the value to subtract from the raw adc value. a value of 0x2000 is typical. 0x19 [15:0] 0x2000 r/w slota_ch2_offset time slot a channel 2 adc offset. the value to subtract from the raw adc value. a value of 0x2000 is typical. 0x1a [15:0] 0x2000 r/w slota_ch3_offset time slot a channel 3 adc offset. the value to subtrac t from the raw adc value. a value of 0x2000 is typical. 0x1b [15:0] 0x2000 r/w slota_ch4_offset time slot a channel 4 adc offset. the value to subtract from the raw adc value. a value of 0x2000 is typical. 0x1e [15:0] 0x2000 r/w slotb_ch1_offset time slo t b channel 1 adc offset. the value to subtract from the raw adc value. a value of 0x2000 is typical. 0x1f [15:0] 0x2000 r/w slotb_ch2_offset time slot b channel 2 adc offset. the value to subtract from the raw adc value. a value of 0x2000 is typical. 0x20 [15:0] 0x2000 r/w slotb_ch3_offset time slot b channel 3 adc offset. the value to subtract from the raw adc value. a value of 0x2000 is typical. 0x21 [15:0] 0x2000 r/w slotb_ch4_offset time slot b channel 4 adc offset. the value to subtract from the ra w adc value. a value of 0x2000 is typical.
data sheet adpd103 rev. b | page 51 of 52 data registers table 26 . data registers address data bits access name description 0x60 [15:0] r fifo_data n ext available word in fifo. prior to reading this register, set the fifo_acces s_ena bit to 0x1 twice with two consecutive write operations to enable fifo access (register 0x5f, bit 0). reset this bit to 0 when the fifo access sequence is complete. 0x64 [15:0] r slota_ch 1_16bit 16- bit value of channel 1 in time slot a. 0x65 [15:0] r slota_ch 2_16bit 16- bit value of channel 2 in time slot a. 0x66 [15:0] r slota_ch 3_16bit 16- bit value of channel 3 in time slot a. 0x67 [15:0] r slota_ ch 4_16bit 16- bit value of channel 4 in time slot a. 0x68 [15:0] r slotb_ ch 1_16bit 16- bit value of ch annel 1 in time slot b. 0x69 [15:0] r slotb_ch 2_16bit 16- bit value of channel 2 in time slot b. 0x6a [15:0] r slotb_ch 3_16bit 16- bit value of channel 3 in time slot b. 0x6b [15:0] r slotb_ch 4_16bit 16- bit value of channel 4 in time slot b. 0x70 [15:0] r slota_ch 1_low low data - word for channel 1 in time slot a. 0x71 [15:0] r slota_ch 2_low low data - word for channel 2 in time slot a. 0x72 [15:0] r slota_ch 3_low low data - word for channel 3 in time slot a. 0x73 [15:0] r slota_ch 4_low low data - word for cha nnel 4 in time slot a. 0x74 [15:0] r slota_ch 1_high high data - word for channel 1 in time slot a. 0x75 [15:0] r slota_ch 2_high high data - word for channel 2 in time slot a. 0x76 [15:0] r slota_ch 3_high high data - word for channel 3 in time slot a. 0x77 [1 5:0] r slota_ch 4_high high data - word for channel 4 in time slot a. 0x78 [15:0] r slotb_ch 1_low low data - word for channel 1 in time slot b. 0x79 [15:0] r slotb_ch 2_low low data - word for channel 2 in time slot b. 0x7a [15:0] r slotb_ch 3_low low data - word for channel 3 in time slot b. 0x7b [15:0] r slotb_ch 4_low low data - word for channel 4 in time slot b. 0x7c [15:0] r slotb_ch 1_high high data - word for channel 1 in time slot b. 0x7d [15:0] r slotb_ch 2_high high data - word for channel 2 in time slot b. 0x7e [15:0] r slotb_ch 3_high high data - word for channel 3 in time slot b. 0x7f [15:0] r slotb_ch 4_high high data - word for channel 4 in time slot b. table 27. required start -u p load sequenc e step number address comment 1 0x4b , bit 7 write to 0x1 to enable the clock that drives the state machine. 2 0x10 write 0x0001 to enter program mode. 3 other registers register order is not important while the device is in program mode. 4 0x10 write 0x0002 to start normal sampling operation.
adpd103 data sheet rev. b | page 52 of 52 outline dimensions 2.70 2.60 sq 2.50 0.80 0.75 0.70 top view exposed pad bot t om view pkg-003523 1 0.40 bsc 28 8 14 15 21 22 7 pin 1 indic at or 0.45 0.40 0.35 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 pin 1 indic at or 0.25 0.20 0.15 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-wgge. 4.10 4.00 sq 3.90 06-23-2015-b 0.20 min fig ure 31 . 28 - lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-28-5) dimensions shown in millimeters bot t om view (bal l side up) a b c d e f 0.560 0.500 0.440 1.44 1.40 1.36 2.50 2.46 2.42 1 2 3 0.300 0.260 0.220 0.40 bsc 0.300 0.225 0.235 2.00 ref bal l a1 identifier 02-03-2015-b sea ting plane 0.230 0.200 0.170 0.330 0.300 0.270 coplanarity 0.05 top view (bal l side down) end view pkg-004659 fig ure 32 . 16 - ball wafer level chip scale package [wlcsp] (cb- 16 - 18 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adpd103bcpz ?40c to +85c 28 - lead lfcsp _wq c p - 28 - 5 adpd103bcpzrl ?40c to +85c 28- lead lfcsp _wq cp- 28 -5 adpd103bcbzrl 7 ?40c to +85c 16- ball wlcsp cb- 16-18 eval - adpd103z - gen ge neric adpd103 evaluation board 1 z = rohs complian t part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2015 C 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12722 -0- 2/16(b)

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